Abstract: A content addressable memory includes a memory array having a plurality of entries. Control circuitry is provided for sequentially presenting each entry in the array to a comparator. An input signal is also provided to the comparator. Entries matching the input signal are identified for later use. The input signal can be masked, so that only selected fields of each entry are compared to it. Conventional RAM technology can be used for the memory array. In the alternative, a serial memory array, such as an array formed from a charge coupled device, can be used.

Abstract: Disclosed is a disc drive system that includes a digital signal processor for processing information sectors read from a CD media. The digital signal processor is configured to parse the information sectors into data frames and subcode frames. A data auto-start unit for triggering a data transfer to a buffer memory when a desired data frame is detected. A subcode auto-start unit for triggering a subcode transfer to the buffer memory when a desired subcode frame is detected. Preferably, the desired data frame and the desired subcode frame have a same MSF. The disc drive system further includes a buffer manager having a plurality of counters that are configured to track the number of data frames and the number of subcode frames being transferred to the buffer memory, and releasing a block including one of the data frames and one of the subcode frames when the counters indicate that the block is complete.

Abstract: An integrated circuit memory including an array of memory cells divided into several sections, and several rows of column decoding amplifiers, the respective outputs of which are interconnected, by column, by means of a decoded bit line, each decoded bit line including two perpendicular sections, one of which is in the row direction to directly connect each decoded bit line to an input of an input-output stage of the memory arranged at one end of the rows.

Abstract: A method is for implementing at least one clock tree in a synchronous digital electronic circuit. The method may include selecting an interchangeable programmable delay buffer stage, calculating an expected skew based upon the selected interchangeable programmable delay buffer stage, and interchanging the selected interchangeable programmable delay buffer stage with another if the expected skew is different from a desired skew. A related synchronous digital electronic circuit includes a plurality of clock trees, and an interchangable programmable delay buffer stage connected to each of the clock trees.

Abstract: A voice coil motor control circuit provides control signals to a voice coil motor circuit drivel that is coupled to a voice coil motor. A current sensing resistor is coupled in series with the voice coil motor. The control circuit includes a sense amplifier having inputs that couple to the current sensing resistor and includes a feedback circuit that includes an input and also includes an output that couples to the voice coil motor driver. In a first mode of operation, the feedback circuit input is coupled to an output of the sense amplifier. The control circuit also includes an inverting operational amplifier. In the first mode of operation, the inverting operational amplifier is bypassed. In a second mode of operation corresponding to deployment of a read/write head from a parked position onto the disc, the inverting operational amplifier is coupled in series between the sense amplifier output and the feedback circuit input.

Abstract: An inertial sensor having an inner stator and an outer rotor that are electrostatically coupled together by mobile sensor arms and fixed sensor arms. The rotor is connected to a calibration microactuator comprising four sets of actuator elements arranged one for each quadrant of the inertial sensor. There are two actuators making up each set. The actuators are identical to each other, are angularly equidistant, and each comprises a mobile actuator arm connected to the rotor and bearing a plurality of mobile actuator electrodes, and a pair of fixed actuator arms which are set on opposite sides with respect to the corresponding mobile actuator arm and bear a plurality of fixed actuator electrodes. The mobile actuator electrodes and fixed actuator electrodes are connected to a driving unit which biases them so as to cause a preset motion of the rotor, the motion being detected by a sensing unit connected to the fixed sensor arms.

Abstract: The memory device comprises a memory array having an organization of the type comprising global word lines and local word lines, a global row decoder addressing the global word lines, a local row decoder addressing the local word lines, a global power supply stage supplying the global row decoder, and a local power supply stage supplying the local row decoder.

Abstract: An error processing circuit for a receiving location of a system for transferring binary data in the form of pulse sequences, wherein the system has a number of receiving locations connected via a double-line bus having a first line and a second line. The circuit includes a data output, a decoder having three decoder outputs, of which a first decoder output associated with both lines delivers a first decoder output signal dependent on the difference between the potential values of both lines, a second decoder output associated with the first line delivers a second decoder output signal dependent on the difference between the potential value of the first line and a first mean potential value, and a third decoder output associated with the second line delivers a third decoder output signal dependent on the difference between the potential value of the second line and a second mean potential value.

Abstract: The manufacturing method comprises, in sequence, the steps of: depositing an upper layer of polycrystalline silicon; defining the upper layer, obtaining LV gate regions of low voltage transistors and undefined portions; forming LV source and drain regions laterally to the LV gate regions; forming a layer of silicide on the LV source and drain regions, on the LV gate regions, and on the undefined portions; defining stack gate regions and HV gate regions of high-voltage transistors; and forming HV source and drain regions and cell regions.

Abstract: A semiconductor memory such as a flash memory, which comprises at least one two-dimensional array of memory cells with a plurality of rows and columns of memory cells grouped in a plurality of packets. The memory cells belonging to the columns of each packet are formed in a respective semiconductor region with a first type of conductivity, this region being distinct from the semiconductor regions with the first type of conductivity in which the memory cells belonging to the columns of the remaining packets are formed. The semiconductor regions with the first type of conductivity divide the set of memory cells belonging to each row into a plurality of subsets of memory cells that constitute elemental memory units which can be modified individually. Thus memory units of very small dimensions can be erased individually, without excessive overhead in terms of area.

Abstract: A method of mounting an electronic component having at least one contact extending across a part of its undersurface may include providing a support smaller in area than the undersurface of the component and having a contact pad for connection to the contact. The contact pad may have a first portion extending across an upper surface of the support adjacent one edge and a second portion extending from the edge across a side surface of the support. The method may also include positioning the electronic component and the support with the undersurface of the component adjacent the upper surface of the support. This is done so that the first portion of the contact pad is aligned with and spaced apart from a first portion of the contact, and the second portion of the contact pad is aligned with and disposed inwardly of a second portion of the contact.

Abstract: A method is for compressing a digital image that is made up of a matrix of elements, with each element including a plurality of digital components of different types for representing a pixel. The method includes splitting the digital image into a plurality of blocks, and calculating for each block a group of DCT coefficients for the components of each type, and quantizing the DCT coefficients of each block using a corresponding quantization table scaled by a gain factor for achieving a target compression factor. The method further includes determining at least one energy measure of the digital image, and estimating the gain factor as a function of the at least one energy measure. The function is determined experimentally according to the target compression factor.

Abstract: A digital-analog converter having a sigma delta cascade modulator with two outputs, particularly a third order sigma delta modulator 2+1.

Abstract: An interconnect system adapted for acting as a data path for transferring data fields on a bus between a plurality of initiators and targets operates in such a way that each data field is transferred during a respective cycle of a corresponding clock signal. The system is configured in such a way that the said data fields are divided into a first and a second part. Similarly, the cycle of the clock signal is divided into a first and a second part. The first and the second part of each data field are transferred, respectively, during the first and the second part of the cycle of the clock signal. Data fields having a size of 128 bits, for example, can thus be transferred on a 64-bit data path structure without any negative effect on the system performance and without the necessity of increasing the clock frequency; this facilitates the integration of the system on a chip.

Abstract: A lateral DMOS transistor having a drain region which comprises a high-concentration portion with which the drain electrode is in contact and a low-concentration portion which is delimited by the channel region. In addition to the conventional source, drain, body and gate electrodes, the transistor has an additional electrode in contact with a point of the low-concentration portion of the drain region which is close to the channel. The additional electrode permits a direct measurement of the electric field in the gate dielectric and thus provides information which can be used both for characterizing the transistor and selecting its dimensions and for activating devices for protecting the transistor and/or other components of an integrated circuit containing the transistor.

Abstract: A microelectromechanical structure, usable in an optical switch for directing a light beam towards one of two light guide elements, including: a mirror element, rotatably movable; an actuator, which can translate; and a motion conversion assembly, arranged between the mirror element and the actuator. The motion conversion assembly includes a projection integral with the mirror element and elastic engagement elements integral with the actuator and elastically loaded towards the projection. The elastic engagement elements are formed by metal plates fixed to the actuator at one of their ends and engaging the projection with an abutting edge countershaped with respect to the projection.

Abstract: A device includes a receiver including an estimation block for estimating the impulse response of the transmission channel and a transformation block. The transformation block may include a preprocessing block for determining a phase minimum transformed impulse response corresponding to a transformed channel based upon the estimated impulse response of the transmission channel, and a filter for filtering the signal received. This makes it possible to retain equality between the autocorrelation of the signal received and the autocorrelation of the filtered signal. Further, the receiver may include an equalizer for applying an equalization processing operation to the filtered signal while taking account of the transformed impulse response.

Abstract: A memory circuit having a first and a second block of memory cells with rows that cross both blocks and columns in each of the two blocks. A word decoder selects one of the rows, and a column decoder selects a set of columns from the first and second blocks. An address splitter passes relative portions of an address to each decoder. In one embodiment, the address splitter passes the most significant bits of the address to the word decoder and passes the remaining bits to a portion of the column decoder coupled to the first block only. The address splitter also modifies the remaining bits, using a bit subtractor, and passes them to a portion of the column decoder coupled to the second block only. A method of operating a memory device is provided that includes accepting an address at an input address circuit and then determining whether the address is for data in the first block or in the second block. This information is assessed by comparing it to the number of memory cells in the first block.

Abstract: A zero crossing control circuit of a bidirectional switch including two transistors of complementary types connected in parallel between the gate of the bidirectional switch and the main reference terminal of the bidirectional switch, the gate of the bidirectional switch being connected to a control source via a first resistor, and each of the control terminals of the transistors being connected to the second main terminal of the bidirectional switch via a second resistor of high value, a zener diode being interposed between the second resistor and each of the control terminals according to a biasing adapted to turning on each of the transistors when the zener threshold is exceeded.

Abstract: Method for localizing point defects causing column leakage currents in a non-volatile memory device including a plurality of memory cells arranged in rows and columns in a matrix structure, source diffusions, and metal lines which connect said source diffusions to each other. Such a method includes the steps of: modifying the memory device in order to make source diffusions independent of each other and each one electrically connected to a respective row; sequentially biasing the single columns of the matrix; localizing the column to which at least one defective cell belongs, as soon as the leakage current flow occurs in the biased column; by keeping biased the localized column, biasing sequentially the single rows of the matrix to the same potential as that of the localized column; localizing a couple of cells, wherein at least one of them involves the point defects, as soon as the leakage current flow does not occur.