Abstract: A preamplifier including an input stage adapted to receiving an analog signal via a connection capacitor, and a differential output stage adapted to providing the signal referenced with respect to a predetermined level, and circuitry for enabling the input stage to accept a signal referenced to the differential stage ground, the signal provided by the output stage being referenced to this ground.

Abstract: A process for manufacturing electronic semiconductor integrated memory devices having a virtual ground and comprising at least a matrix of floating gate memory cells is presented. In the memory device, the matrix is formed on a semiconductor substrate with a number of continuous bit lines extending across the substrate as discrete parallel strips. The process begins by growing an oxide layer over the matrix region and depositing over the semiconductor throughout a stack structure which comprises a first conductor layer, a first dielectric layer, and a second conductor layer. Then a second dielectric layer is deposited over the stack structure, and floating gate regions are defined by photolithography using a mask of “POLY1 along a first direction”, to thereby define in the dielectric layer, a plurality of parallel strips which delimit a first dimension of floating gate regions.

Abstract: Presented is a ferroelectric non-volatile memory cell in a semiconductor substrate that has a MOS device connected in parallel to a ferroelectric capacitor. The MOS device has first and second conduction terminals and is covered with an insulating layer. The ferroelectric capacitor has a lower electrode formed on the insulating layer above the first conduction terminals and are electrically coupled to them. The lower electrode of the ferroelectric capacitor is covered with a layer of ferroelectric material and coupled capacitively to an upper electrode. The upper electrode is formed above the second conduction terminals and are electrically connected thereto, and extends over the ferroelectric material to at least partially overlap the lower electrode. Also presented is a non-volatile memory matrix that includes a plurality of the ferroelectric memory cells that are organized into rows and columns.

Abstract: A test mode structure and method of a multi-power-source device provides for the device to remain in a test mode, during which current draw of the device may be accurately measured, even after primary power supply to the device has been greatly reduced or completely removed. Significant reduction or removal of the primary power supply while still remaining in the test mode is necessary to counter the presence of a variable current that would otherwise be normally generated by the multi-power-source device in the test mode; the presence of the variable current during the test mode, if not negated, will not permit an accurate measurement of the current draw of the multi-power-source device. Significant reduction or removal of the primary power supply to the device would typically cause the multi-power-source device to exit the test mode and switch to a secondary supply voltage supplied by the secondary power supply, thereby foiling any attempt to measure the current draw of the device.

Abstract: When programming, for each programming pulse, a threshold voltage whose value is increased with respect to the previous programming pulse is applied to the gate terminal of each cell to be programmed. After an initial step, the increase of threshold voltage of the cell being programmed becomes equal to the applied gate voltage increase. In order to reduce the global programming time, keeping a small variability interval of threshold voltages associated with each level, to pass from a threshold level to a following one, each cell to be programmed is supplied with a plurality of consecutive pulses without verify, until it is immediately below the voltage level to be programmed, and then a verify step is performed, followed by subsequent programming and verify steps until the cell to be programmed reaches the desired threshold value.

Abstract: An amplifier circuit including at least one first input amplifier; at least one second amplifier cascode-assembled with the first amplifier; and at least one reactive impedance circuit, mounted in series with the second amplifier, the reactive impedance circuit being formed by two impedances respectively exhibiting a maximum value for a first and a second frequency, to form a double-band amplifier circuit.

Abstract: A multi-carrier transmission system, for example a DMT system. Channel information is transmitted between two transceivers using a plurality of subcarriers. Each subcarrier, or symbol, has a parameter associated with it. The transceivers are adapted to transmit the channel information as a sequence of n groups in which each of the n groups contains information concerning the number of adjacent subcarriers which have the same value as the parameter, together with the actual value of the parameter. The parameter which may have a plurality of discrete values, may be a bit-loading value, or a QAM constellation identifier.

Abstract: Disclosed is a bootstrap circuit in DC/DC static converters having the characteristic of comprising a fixed frequency signal, a recharge circuit of a capacitor and current generator means, said generator means controlled so as to emit current pulses, in synchrony with said fixed frequency signal, of a predetermined duration, every time that charge accumulated by said capacitor goes below a predetermined level.

Abstract: An integrated self-powered and switching electronic circuit regulates a stable reference voltageand comprises a band-gap voltage generator to produce said stable reference voltage for a system circuit block that is generally supplied by the output of the band-gap generator through a comparator and an error amplifier. A regulating loop is provided between the output of the system block and the input of the voltage generator circuit to supply a voltage signal produced by the output of the system block. Advantageously, the voltage generator circuit incorporates both the comparator and the error amplifier.

Abstract: A PWM power amplifier having at least one PCM/PWM converter fed by PCM digital input signals and producing PWM digital output signals, and at least one power amplification final stage of the PWM digital output signals. At least one PCM/PWM converter includes a counter fed with at least one clock signal produced by a clock generator device and having a digital comparator suitable for comparing the PCM digital input signals of at least one PCM/PWM converter with a digital comparison signal produced by the counter and producing in output the PWM digital signals. The clock generator device includes a pulse generator device and an oscillator; the pulse generator device receives a signal at a frequency that is equal to the frequency of the PCM digital input signals of the at least one PCM/PWM converter and produces in output reset pulses. The reset pulses are sent in input to the oscillator, which produces in output the at least one clock signal.

Abstract: A decoder with reduced complexity includes at least one OR circuit section and at least one AND circuit section. The at least one OR circuit section may include first and second circuit lines mutually connected and respectively receiving as inputs an address signal and an inverted address signal. The at least one AND circuit section may include first and second circuit lines which respectively receive as inputs the inverted address signal and the address signal. The at least one OR circuit section and the at least one AND circuit section may be connected to first and second booster circuits. Furthermore, the at least one OR circuit section may also include a virtual ground.

Abstract: An output circuit which can minimize the delay in combining two clocks comprises a multiplexer with a flip flop connected to one input and a clocked latch connected to the other. The clocked latch is transparent during one clocking state so that changes to its input appear directly at its output.

Abstract: An active pull-up circuit for connection to an input pin that receives high and low logic level signals and a high voltage signal whose level is higher than the high logic level. The active pull-up circuit includes a pull-up circuit that is coupled between the input pin and a voltage supply line, and a breaking circuit that is coupled between the pull-up circuit and the voltage supply line. The pull-up circuit selectively brings the input pin to the level of the voltage supply line, and the breaking circuit operates to inhibit the pull-up circuit when the high voltage signal is on the input pin. In a preferred embodiment, the breaking circuit inhibits the pull-up circuit by electrically isolating the pull-up circuit from the voltage supply line. A method for selectively pulling-up an input node is also provided.

Abstract: A process for forming, on a semiconductor substrate, an isolation structure between two zones of an integrated circuit wherein active regions of electronic components integrated thereto have already been defined, comprises the steps of: defining an isolation region on a layer of silicon oxide overlying a silicon layer; selectively etching the silicon to provide the isolation region; growing thermal oxide over the interior surfaces of the isolation structure; depositing dielectric conformingly; and oxidizing the deposited dielectric.

Abstract: A method is provided for driving a brushless motor of a type including windings pre-connected in a star or polygon configuration with an integrated driving system designed for independently driving the phase windings. The integrated driving system includes a plurality of output pins corresponding to the output nodes of as many half-bridge stages that are driven in pairs respectively by a direct or inverted driving signal at the same power level without overloading the output metal lines of the integrated device. Each supply terminal of the brushless motor is connected to one of the plurality of output pins of the integrated system relative to a first driving phase signal and to another output pin relative to a different driving phase signal. The drive circuit is internally configured through a plurality of integrated signal path selectors set in one or the other position depending upon the intended use of the integrated device.

Abstract: A voltage regulator includes a capacitor providing a regulated voltage, a regulation switch for connecting the capacitor to a voltage source, and a regulation circuit for closing the regulation switch when the regulated voltage is below a first reference voltage. The voltage regulator also includes at least one ballast switch arranged in parallel with the regulation switch. The regulation circuit opens the regulation switch and closes the ballast switch during a starting phase of the regulator.

Abstract: An alphanumeric character image recognition system includes a first stage comprising at least a first, second and third digital image signal processing network having each at least one input terminal and at least one output terminal and said networks being designed to process image information from digital image signals, and comprising at least a first, second and third memory register having each at least one input terminal and at least one output terminal and the input terminals of the first, second and third memory registers being connected to the output terminal of the first network, the output of the second network and the output terminal of the third network respectively and said memory registers being designed to contain the image information processed by the first, second and third digital image signal processing networks, and a second stage characterized in that said second stage comprises at least one first and one second classifier network having each at least one first and one second input termina

Abstract: A switched capacitor integrator particularly suitable to realize low-pass filters without inducing noise on the nodes of the reference potentials of the integrator, is provided by halving the input capacitance during an operating phase, and by transferring the electric charge between the input switched capacitance and the capacitor of integration of one and the other feedback branch of the differential amplifier, in a direct manner, that is, not referred to a fixed common potential. A unique current path is established, thus averting the effects caused by inevitable mismatches between the integrated capacitors.

Abstract: A submicrometer vertical-channel MOSFET of high quality and reproducibility is produced by a method compatible with DPSA technology. The method steps are performed on a wafer of semiconductor material having a layer with n conductivity. First, n impurity ions and p impurity ions are implanted in an area of the layer and the wafer is subjected to a high-temperature treatment. The impurities, the implantation doses and energies, and the high-temperature treatment time and temperature being such as to form a first p region, and a second n region which forms a pn junction with the first region. A trench is hollowed out which intersects the first region and the second regions.

Abstract: An LED driver circuit and method are disclosed where an array of light emitting diodes have a transistor connected to each respective array of light emitting diodes. A PWM controller has an input for receiving a voltage reference and an output connected to selected transistors for driving selected transistors and setting a PWM duty cycle for the selected arrays of light emitting diodes to determine the brightness of selected light emitting diodes. An oscillator is connected to the PWM controller for driving the PWM controller.