Abstract: Apparatus, methods, systems and computer program products are disclosed describing a data structure and associated processes that optimize garbage collection techniques. The disclosed data structure can be used as an instantiated object in an object-oriented programming environment. The data structure uses a data structure header to separate the portion of the data structure that contains pointer values from the portion of the data structure that contains non-pointer values. The contents of the first word of the data structure header is distinguishable from any pointer value. Thus, a garbage collection procedure can more rapidly locate the pointer values in the data structure. Another advantage of this data structure organization, when applied to instantiated objects, is that the position of an instance variable (with respect to the object header structure) remains constant for all instantiated objects including those based on subclasses of the original class.

Abstract: A float register spill cache method for improving the efficiency of usage of floating point single precision registers computer using a microprocessor conforming to the SPARC-V9 architecture specification. Values are temporarily stored in a plurality of double precision registers which are utilized as a float spill cache having a plurality of float spill slots. Values are generally shifted from one of the single precision registers to a second single precision register which is used as a spill pad, and then from the spill pad to a selected one of the float spill slots.

Abstract: The disclosed invention relates to the employment of a spacer element for mounting, aligning and spacing a computer chip relative to a PCB. The spacer element is formed and dimensioned to engage the chip in a manner to assure that the pins of the chip are properly aligned relative to openings in the PCB and to assure that the chip is centered and maintained parallel to the PCB and each of its pins maintained equal distance from the underneath side of the PCB during the wave soldering process for electrically connecting the chip and PCB.

Abstract: A circuit is disclosed which allows an IN-Test to be performed on an integrated circuit (IC) without having to stop the external clock sources by disabling the IC's internal phase-locked loops. Information indicative of the IC's clock mode and of the desired stop mode is contained within the IC's clock control register. In one embodiment, the internal clocks may be stopped in either of three stop modes while operating in one of three clock modes. When it is desired to stop the IC's internal clocks, the clock control register provides a stop instruction signal STOP.sub.-- INSTR to a clock control circuit which, depending upon the particular stop mode and clock mode encoded in signal STOP.sub.-- INSTR by the clock control register, asserts a enabling signal to a disable clock circuit.

Abstract: A Java.TM.-to-Database Connectivity Server monitors client communications, accesses a database such as a Sybase relational database, upon client command establishes a connection to the database, accesses requested data from the database, manipulates the data, and relays the data to the client. The Java.TM.-to-Database Connectivity Server is programmed in the Java.TM. programming language to facilitate communications with Java.TM. clients using Java.TM. sockets. The Java.TM.-to-Database Connectivity Server includes an Applications Programmer Interface (API) on the server side of a client/server interface and implementation of System Query Language (SQL) queries on the client side. The Java.TM.-to-Database Connectivity Server supplies an interface between Java.TM. applications and database servers using an easy-to-use Java.TM. server Applications Programmer Interface (API) forming a uniform framework for building or integrating database connectivity across organizations and companies globally.

Abstract: A technique for managing address translation storage buffers (TSBs) supports multiple pools of different TSB sizes and dynamically assigns a process to its own TSB of the proper size as the needs of the process change. A process is assigned a small TSB and the system migrates the process to a larger TSB if needed. One method includes the steps of identifying sizes of TSBs to support, allocating a TSB pool in memory with these sizes, selecting an appropriately sized TSB for a process, and migrating that process to a larger size should the process require more memory. A second method allocates a TSB pool by determining an appropriate size for the TSB pool, determining sizes of TSBs to support, allocating memory for the pool and initializing status block for each size of TSB. A third method selects an appropriate TSB for a process by selecting a smallest supported size of a TSB from the pool.

Abstract: An integrated processor/memory device comprising a main memory, a CPU, a victim cache, and a primary cache. The main memory comprises main memory banks. The victim cache stores victim cache sub-lines of words. Each of the victim cache sub-lines has a corresponding memory location in the main memory. When the CPU issues an address in the address space of the main memory, the victim cache determines whether a victim cache hit or miss has occurred in the victim cache. And, when a victim cache miss occurs, the victim cache replaces a selected victim cache sub-line of the victim cache sub-lines in the victim cache with a new victim cache sub-line. The primary cache comprises primary cache banks. Each of the primary cache banks stores one or more cache lines of words. Each cache line has a corresponding memory location in the corresponding main memory bank.

Abstract: An atomic instruction is executed without the use of a dedicated atomic unit. A store instruction is transmitted from a front-end of one of a plurality of processors to a write-cache to cause the write-cache to obtain exclusive access to a control memory of a shared resource. A first signal is then transmitted to the front end of the processor indicating that the write-cache has obtained exclusive access to the control memory of the shared source. At least one next instruction is executed, and a second signal is transmitted from the front end to the write cache indicating that execution of the at least one next instruction has been completed. Data from the write cache is stored in the control memory of the shared resource in response to the second signal transmitted to the write cache.

Abstract: The presentation of audio information, particularly audio information generated by a voice synthesizer from text using a text or screen reader, is controlled using a style sheet. The style sheet permits default presentation styles, such as voice-family, voice-pitch, voice-variant, voice speed and volume to be set, and then varied based on embedded text presentation commands such as those found in hypertext markup language and in desktop publishing.

Abstract: Allocation of real registers to virtual or symbolic registers represented by nodes in an interference graph is performed with a compiler using a primary interference graph and a secondary interference graph. The primary interference graph contains the standard edges indicating latency between virtual registers represented by nodes linked by the edges. Secondary links between nodes indicate conditional conflicts which can be tolerated but which, if avoided in the register allocation process, improve the execution speed of program segments. The conditional conflict specifically referenced is the requirement for paired register designation in single precision floating point operations in which registers are identified as pairs, rather than as individual registers.

Abstract: A new register test system and method is provided for testing a register. The register under test has a number of bit storage locations, each of which is associated with one of a plurality of categories, including, for example, a read/write category, a read-only category, a write-only category, an always-"1" category and an always-"0" category. In accordance with the method, in each of a plurality of iterations, a data word is generated, stored it in the register under test, and thereafter retrieved from the register. For each iteration, an expected pattern is generated for comparison to the retrieved contents, using the original data, the retrieved contents and a plurality of mask patterns each associated with one of the categories. The expected pattern is compared to the pattern of the contents retrieved from the register and whether the register is deemed to be operating properly can be determined by whether the expected pattern corresponds to the retrieved pattern.

Abstract: A driver includes first and second input terminals for receiving first and second input voltages, respectively, of a differential input signal, first and second switches coupled to the first and second input terminals, respectively, third and fourth switches coupled to the first and second input terminals, respectively, first, second, third and fourth current references coupled to the first, second, third and fourth switches, respectively, first second, third and fourth current mirrors coupled to the first, second, third and fourth current references, respectively, a first output terminal coupled to the first and third current mirrors, and a second output terminal coupled to the second and fourth current mirrors.

Abstract: A multiprocessing computer system employing a three-hop communications protocol including a reply count communication. When a request is sent by a requesting node to a home node, the home node sends read and/or invalidate demands to any slave nodes holding cached copies of the requested data. The demands from the home node the slave nodes may each advantageously include a value indicative of the number of replies the requesting agent should expect to receive. The slaves reply back to the requesting node with either data or an acknowledge. Each reply may further include the number of replies the requester should expect. Upon receiving all expected replies, the requesting node may send a completion message back to the home and may treat the transaction as completed and proceed with subsequent processing.

Abstract: Apparatus, methods, systems, and computer program products are disclosed for displaying fixed canvas presentations, defined using HTML data, on computer output devices of unknown sizes. The invention transforms the fixed canvas image to fit within a display view that of a size other than that of the display view used to construct the original image. This transformation maintains a page layout similar to that of the original but magnified or reduced to fit the available display area.

Abstract: A circuit for locally ensuring mutual exclusivity of selected signals during scan testing is coupled between an IEEE 1149.1 TAP controller and a conventional gating circuit. The mutual exclusivity circuit includes an AND-gate, an inverter, a first scan flip-flop and a second scan flip-flop. The first and second flip-flops have their scan-input leads hardwired to receive logic "1" and logic "0" signals, respectively. The first flip-flop also has its data input lead hardwired to receive a logic "0" signal. During the scan mode, the AND-gate receives a conventional rst.sub.-- tri.sub.-- en signal from the TAP controller. Thus, the AND-gate outputs a local.sub.-- rst.sub.-- tri.sub.-- en signal identical to the rst.sub.-- tri.sub.-- en signal. After the test pattern is scanned in, the rst.sub.-- tri.sub.-- en signal transitions to a logic "1" level, causing the local.sub.-- rst.sub.-- tri.sub.

Abstract: A method and apparatus for providing a translation environment for a computer system. Structurally, the present invention includes three main components: a codeset manager, a codeset database, and a codeset translation engine. The codeset manager compiles a set of codeset definitions. The compiled codeset definitions, or translation methods, are included in a codeset database. To translate a character, a client process requests the translation, specifying a source codeset and a target codeset from the codeset translation engine. The codeset translation engine transmits the requested translation to the codeset manager which searches the codeset database for an appropriate translation method. If no appropriate translation method exists in the codeset database, the codeset manager may be able to create a translation method using one or more translation methods in the codeset database.

Abstract: In a multiprocessor computing system, virtual memory addresses are mapped to local physical memory addresses of an attraction memory, containing a replication of the data contained at remote physical addresses, in a node of the system. A mapping table is created and maintained in each node of the system to supplement a conventional page table. The mapping table is used to map a global physical address to a local physical address of the replicated page of memory. System performance is enhanced by subsequent access to the data stored at the local physical address, as opposed to the remote physical address.

Abstract: A method and apparatus for fast rendering of objects or scenes on a display controlled by a computer system. The scene to be rendered is stored as a series of triangle lists in an object data file. The triangle lists are presorted by the system into front- and back-facing triangles, as determined by scalar products of the triangle's normal vector with a vector from each respective triangle to the user's selected viewpoint. An array of pointers is generated for the front-facing triangles, and another array is generated for the back-facing triangles. The object or scene is rendered by first loading the attributes for the front-facing triangles to a frame buffer controller, then processing all of the front-facing triangles sequentially, without switching back and forth between front- and back-facing triangles. The attributes for the back-facing triangles are then loaded, and the back-facing triangles are then all processed sequentially.

Abstract: In a multiprocessor system, a method, apparatus, and article of manufacture for maintaining the proper sequence of store/write operations between multiple processors to remote I/O devices without requiring changes to application software. A synchronizer is employed to synchronize write operations to the remote I/O device, and the write operations are synchronized individually upon detection and emulation, or as a group upon detection of the release of a mutual exclusion lock.

Abstract: A flip-flop circuit with scan circuitry for use with static logic gates includes a dynamic input stage and a static output stage. The dynamic input stage is coupled to receive a data signal, a scan input signal, a scan enable signal, a data enable signal and a single-phase clock signal. During the precharge phase, the dynamic input stage provides an output signal that is the complement of the data or the scan signal. The dynamic input stage output signal is precharged to a logic high level during the precharge phase. During the precharge phase, the static output stage maintains the flip-flop output signal logic at the logic level of the previous evaluation phase independently of the signal received from the dynamic input stage. During the evaluation phase in the normal mode, the dynamic input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low, complementing the logic level of the data signal.