Abstract: Apparatus, methods, systems and computer program products are disclosed that detect when a user is interested in information presented on a display device. The invention then automatically presents additional information to the user about the information presented on the display device.

Abstract: An apparatus for executing an instruction is provided. The instruction loads data into one of a plurality of registers in a register file and is in a first group of instructions. A second group of instructions is executed sequentially after the first group of instructions. The first and second groups of instructions should each include at least one instruction. The apparatus includes a first memory, a second memory, a first functional unit coupled to the first memory, and a second functional unit coupled to the first memory and to the second memory. The first and second functional units are both capable of executing the instruction. Also included is an instruction issue unit coupled to the first and the second functional units. The instruction issue unit issues the instruction to a selected functional unit selected from one of the first and the second functional units. This selection is based on a load prediction bit associated with the instruction.

Abstract: In a processor executing instructions speculatively or out-of-order, a dependency table tracks instruction dependencies between a current instruction and a live instruction. The table contains an instruction identifier and the destination register specified by the live instruction. The table can also contain information about the age of the entry, the validity of the entry, and the process which the entry is associated. A dependency between instructions is determined by one or more comparators comparing the destination register to the source registers of the current instruction. True dependencies are distinguished from false dependencies using the age information, the validity information, and the process information.

Abstract: A method and system for organizing selectable elements on a graphical user interface (GUI). Initially, the method provides at least two selectable elements for display on a GUI. Each selectable element is associated with a target element when it is selected. The method generates a first access frequency index for each selectable element in the list which corresponds to a number of times the selectable element is selected. Next, the selectable elements are organized on the GUI based upon the first access frequency index generated for each selectable element. In one embodiment, the selectable elements with a higher first access frequency index are placed in first area on the GUI while selectable elements with a lower first access frequency index are placed in a second area on the GUI. As a result, a user can select the selectable elements on a GUI easier when they are organized according to the principles of this invention.

Abstract: A method for handling an underflow condition in a processor is disclosed. A first plurality of signal data is packed into a first memory location so as to form a first word. A second plurality of signal data is packed into a second memory location so as to form a second word. A bitwise operation is then performed between the first word and the second word to produce a result. The result of the operation is then stored in a k bit memory location so as to form a third word. A bit mask is then obtained by arithmetic shifting the third word right (k-1) bits. The bit mask is then inverted. A logical AND operation is then performed between the inverted bit mask and the result.

Abstract: An apparatus for allowing a RAM array within an SRAM to be tested via scan ATPG is disclosed. A first clocked flip-flop has a data input latched high, a scan-in input latched high, a clock input coupled to a signal source generating a periodic waveform, a scan-enable input coupled to a scan enable signal, and an output. The first flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high. A second clocked flip-flop has a data input coupled to the output of the first flip-flop, a scan-in input latched high, a clock input coupled to the signal source, a scan enable input coupled to the scan enable signal, and an output. The second flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high.

Abstract: A cross-domain data transfer technique is disclosed in which page remapping operations are eliminated in situations where physical memory addresses can be passed across domains. By passing physical memory addresses across domains instead of virtual memory addresses, the page remapping operations necessarily associated with passing virtual memory addresses across domains can be avoided in many cases. With the receipt of data across domains, page remapping operations are able to be deferred until the data is received in a domain that needs to touch the data. In certain cases, the transfer of data can be completed without ever having to map in the data to the receiving domain's address space. With the transmission of data across domains, where possible the pages are borrowed in their physical form. The invention can be embodied in many ways, including system, apparatus or method forms.

Abstract: A method and apparatus for displaying graphics data and video data, such as a video window, on a computer display. A graphics adapter chip stores graphics pixel data in a graphics memory, and a video source stores video pixel data in a video memory. The graphics and video memories sequentially output blocks of pixel data to the display screen on output channels. Graphics data is selectively outputted on a number of graphics channels and video data is selectively outputted on the same number of video channels. The video channels are multiplexed with the graphics channels to form the output channels and either graphics data or video data can be output to the display on each output channel. A number of dummy video pixel values can be inserted before video data in the video memory to align video pixels between blocks of graphics data on the display screen.

Abstract: An embodiment of the present invention provides an improved method and system for synchronizing the execution of two or more events used to test a software product. The improved method begins by invoking a driver to assist in the generation of a first event. The driver program sends over a first message which instructs the client to initiate generation of the first event. After the first event has been generated, the client stores the first event in a first buffer. Next, the client processes the first event. In the course of processing the first event, other events may have been generated and stored in the first buffer. Therefore, the client examines the first buffer to determine if events spawned while processing the first event await processing. If new events are stored in the first buffer, then the client processes the new events. This process continues until the examination determines that the first buffer does not store events.

Abstract: A fault tolerant memory control system is provided for a computer system having a host processor, a memory and a system interconnect. The memory control system includes a primary memory controller and a backup memory controller with a tap coupled to the interconnect. Data is transferred from the host processor to the memory in the form of data packets. First, the host processor writes to the memory by sending a data packet to the primary memory controller which then caches the data from the data packet. The backup memory controller taps the interconnect to obtain a backup copy of the data packet as the data packet is being sent from the host processor to the primary memory controller which caches the data from the backup copy of the data packet. If the primary memory controller is functional, the primary memory controller sends the data to the memory via a primary path coupling the primary memory controller to the memory. Conversely, if the primary memory controller fails, i.e.

Abstract: The present invention provides a method and system for regulating discounts on merchandise distributed through networked computer systems. The method and system involve the use of discount coupons valid toward the repurchase of the merchandise. These discount coupons include mechanisms for verifying the validity of the coupons. A system in which the present invention operates includes a vendor computer system and a user computer system connected via a network. The vendor and user computer systems each include a computer connected to a display device, a keyboard, and a secondary storage device. A vendor discount regulator and a user discount regulator are stored in the vendor/user secondary storage devices for execution by the vendor/user computers. In operation, when a user desires to purchase merchandise, the user creates a request to purchase the merchandise and sends the request to purchase to a vendor.

Abstract: A bar code reader, a wireless transceiver, an earphone jack and a battery are integrated into a pen sized device. The bar code reader is used to scan the product identification code or music packaging. The product code is sent to a central computer or a music store where one or more stored digital samples of the music reside in a database. One or more music samples are retrieved and sent to the pen sized device where the sample is converted to audio signals for listening by a user over the earphone jack.

Abstract: A system for maintaining completion order in a multiple bus system including a bridge that posts write data includes logic units for implementing a DRAIN/EMPTY protocol. A bridge logic unit asserts an EMPTY signal when the secondary posting buffers are empty. Interrupt processing is delayed until the EMPTY signal is asserted thereby assuring that all writes are completed. If an interrupt is received and the EMPTY signal is not asserted then a DRAIN signal is asserted while the EMPTY signal is not asserted. The bridge retries all upstream write requests until EMPTY is asserted.

Abstract: According to a presently preferred embodiment of the present invention, a method for processing a incoming signal comprising the steps of selecting from a first signal a first plurality of bits of signal information to be processed, selecting from a second signal a second plurality of bits of signal information to be processed, reading the first plurality of bits of signal information into contiguous memory space so as to form a first word, reading the second plurality of bits of signal information into contiguous memory space so as to form a second word, causing a first logical AND operation to be performed on the second word with a mask, causing a first logical OR operation between the first word and the complement of the mask, causing a first EXCLUSIVE OR operation between the first word and the complement of the second word, causing a second logical AND operation between the results of the first EXCLUSIVE OR operation and the complement of the mask, subtracting the results of the first logical AND operati

Abstract: During processing, such as wave soldering, it is necessary to support a printed circuit board (PCB) above a pallet or carrier without sagging. A support rod has hooks which fit through holes in the PCB and engage the margins of the holes. Ends of the rod are provided with second hooks which engage the pallet or carrier to support the rod above the pallet and thereby support the PCB. Preferably the rod is multi-sectional and spring biased so that the hooks may be conveniently installed in the holes.

Abstract: A graphical user interface (GUI) application program has one or more screens and a number of objects hereinafter "field objects", each field object being uniquely associated with a single field in a screen. Each field object contains storage elements that hold data displayed in a screen's field. Each field object also contains storage elements that indicate functions that can be performed on data held in the field object. The field object may have at least three data member storage elements, one for holding data, another for holding a label, and yet another for holding a search operator. The GUI application program also includes field map storage elements, each of which maps a field in a screen to a corresponding column in the database, thereby allowing database queries to be created and performed dynamically on user entered field information. Such field map storage elements allow a database to be changed without affecting various parts, e.g. field objects and screen functions, of the GUI application program.

Abstract: The present invention provides a hybrid Non-Uniform Memory Architecture (NUMA) and Cache-Only Memory Architecture (COMA) caching architecture together with a cache-coherent protocol for a computer system having a plurality of sub-systems coupled to each other via a system interconnect. In one implementation, each sub-system includes at least one processor, a page-oriented COMA cache and a line-oriented hybrid NUMA/COMA cache. Such a hybrid system provides flexibility and efficiency in caching both large and small, and/or sparse and packed data structures. Each sub-system is able to independently store data in COMA mode or in NUMA mode. When caching in COMA mode, a sub-system allocates a page of memory space and then stores the data within the allocated page in its COMA cache. Depending on the implementation, while caching in COMA mode, the sub-system may also store the same data in its hybrid cache for faster access.

Abstract: A method and apparatus for compiling source code that pre-evaluates certain semantic attributes during syntactical analysis. The invention performs certain type of semantic analysis, such as checking semantic attributes, during the operation of the syntactical analyzer, while the parse tree is being built, instead of waiting to perform these checks in a separate pass through the parse tree during semantic analysis. The present invention modifies the format of nodes in the parse tree to include fields for semantic attributes and modifies the actions associated with grammar productions so that they create parse tree nodes of the correct format. In addition, the present invention includes semantic attribute routines that determine the attribute values to store in the parse tree for the various semantic attributes.

Abstract: A hybrid compiler-interpreter comprising a compiler for "compiing" source program code, and an interpreter for interpreting the "compiled" code, is provided to a computer system. The compiler comprises a code generator that generates code in intermediate form with data references made on a symbolic basis. The interpreter comprises a main interpretation routine, and two data reference handling routines, a dynamic field reference routine for handling symbolic references, and a static field reference routine for handling numeric references. The dynamic field reference routine, when invoked, resolves a symbolic reference and rewrites the symbolic reference into a numeric reference. After rewriting, the dynamic field reference routine returns to the main interpretation routine without advancing program execution to the next instruction thereby allowing the rewritten instruction with numeric reference to be reexecuted.