Abstract: An efficient streamlined cache coherent protocol for replacing data is provided in a multiprocessor distributed-memory computer system. In one implementation, the computer system includes a plurality of subsystems, each subsystem includes at least one processor and an associated cache and directory. The subsystems are coupled to a global interconnect via global interfaces. In one embodiment, when data is replaced from a requesting subsystem, an asynchronous flush operation is initiated. In this implementation, the flush operation includes a pair of decoupled local flush instruction and corresponding global flush instruction. By decoupling the local flush instructions from the global flush instructions, once the requesting processor in the requesting subsystem is done issuing the local flush instruction, the requesting processor does not have to wait for a corresponding response from home location associated with the data being replaced.

Abstract: A method and apparatus for representing and storing the schedules of recurring events. The schedules are represented by recurrence rules generated according to a specific grammar. According to the grammar, each recurrence rule is composed of one or more recurrence commands. Each recurrence command corresponds to a cycle and includes a time interval indicator that specifies the duration of the cycle and a repeat quantity that determines the number of times the cycle is repeated in the schedule. Each recurrence command may also include an occurrence list that specifies at what times during a particular cycle the event occurs. The occurrence list may specify times in absolute or relative terms. Thus, the grammar supports recurrence rules for representing the schedule "first and tenth of every month" as well as the schedule "second Thursday and last Friday of every month".

Abstract: An integrated processor includes an on-chip integrated input/output (IO) system (which does not have a on-chip bus) to handle direct memory access (DMA) operations from external IO units and interface with external cache and main memories. The integrated IO system includes an external cache controller that controls access to both the cache and main memory so as to maintain coherency between the cache and main memory. As part of maintaining data coherency, the cache controller prevents race conditions between instructions generated from a core logic unit within the microprocessor and DMA instructions generated from an external IO unit by giving the DMA request priority over the CPU instructions.

Abstract: A test support tool system and method produce software test programs from a logical description of selected software. Test programs are created by producing a cause-effect graph from the logical description, creating a decision table, producing test cases, and synthesizing test cases into a test program. The test support tool system includes an interface for receiving a logical description of software, a logical database, an analysis and test case generation module, a control module, and a test program synthesis module.

Abstract: A system for generating and maintaining lock files to inhibit conflicting requests for data files. A first process that accesses a data file generates a lock file to prohibit other processes from reading and/or writing that data file. Periodically the first process refreshes the lock file so that it shows a new modification time. A second process requesting access to the data file detect the lock file, stores the time of the attempted access, then waits a predetermined wait period and reads the lock file again. This is repeated, each time waiting for the wait period and again reading the lock file, until either (1) a predetermined time-out period passes without the first process refreshing the lock file, whereupon it is presumed that the process is defunct so the second process may access the data file; or (2) more than a maximum allowed access period of time has passed without the second process gaining access, i.e. the first process continues to refresh the lock file for greater than some predefined period.

Abstract: An efficient cache allocation scheme is provided for both uniprocessor and multiprocessor computer systems having at least one cache. In one embodiment, upon the detection of a cache miss, a determination of whether the cache miss is "avoidable" is made. In other words, would the present cache miss have occurred if the data had been cached previously and if the data had remained in the cache. One example of an avoidable cache miss in a multiprocessor system having a distributed memory architecture is an excess cache miss. An excess cache miss is either a capacity miss or a conflict miss. A capacity miss is caused by the insufficient size of the cache. A conflict miss is caused by insufficient depth in the associativity of the cache. The determination of the excess cache miss involves tracking read and write requests for data by the various processors and storing some record of the read/write request history in a table or linked list. Data is cached only after an avoidable cache miss has occurred.

Abstract: Symmetry in a filter is used to reduce the complexity of an interpolator or a decimator. A weight filter matrix which includes L=(N-1)M+K weights is divided into two sub-filters, the first having L1=NK weights and the second having L2=(N-1)(M-K). For interpolators, N source samples are applied to the first sub-filter to produce K signals and N--1 source samples are applied to the second sub-filter to produce M-K signals. For decimators, K source samples are applied to the first sub-filter to produce N samples and M-K source samples are applied to the second sub-filter to produce N-1 samples. An inverse relationship is recognized when a first weight is associated with a first of the samples and a second weight with a second of the samples and a weight equivalent to the first weight is associated with the second sample and a weight equivalent to the second weight is associated with the first sample. Two composite weights of the first and second weights and composite sample signals weighted therewith are formed.

Abstract: An applications programming interface 20 to a telecommunications management network includes a command language interpreter 24 and a compiler 40. A command string input/output format is provided, the command strings 42 including network management parameters. The interpreter includes interpreter scripts for converting the network management parameters between the command string format and a network management protocol compatible format. The compiler compiles interpreter scripts for encoding and decoding user defined parameter types, which are then loaded dynamically to the interpreter. The interface provides a convenient "command line" API, while at the same time permitting extensions to the interpreter in a dynamic manner.

Abstract: A cache, storing misspelled or otherwise incorrect network addresses from a plurality of users and associated correct network addresses, is maintained at a proxy server or internet service provider. Addresses received from all users are checked against the cache to correct any misspellings or other situations in which the network address might be incorrect. The cache is periodically pruned of entries which aren't frequently used. The collective experience of a group of users can thus be utilized to correct a network address submitted by a user who has never visited a particular network address before.

Abstract: A computer system optimized for block copy operations is provided. In order to perform a block copy from a remote source block to a local destination block, a processor within a local node of the computer system performs a specially coded write operation. The local node, upon detection of the specially coded write operation, performs a read operation to the source block in the remote node. Concurrently, the write operation is allowed to complete in the local node such that the processor may proceed with subsequent computing tasks while the local node completes the copy operation. The read from the remote node and subsequent storage of the data in the local node is completed by the local node, not by the processor. In one specific embodiment, the specially coded write operation is indicated using certain most significant bits of the address of the write operation.

Abstract: A computer system has a CPU, a stack cache and a main memory. The main memory is a conventional untagged memory, where each memory location is a word having a bit size that is an integer power of 2 (e.g., 32, 64 or 128 bits per word). However, at least one stack cache associated with the CPU (and preferably integrated with the CPU on the same semiconductor circuit or in the same chip set) is a tagged memory where each data word of the stack cache has an associated tag. Whenever the stack cache overflows with data, at least a portion of the contents of the stack cache are stored in a previously established location in main memory so as to make room for storing additional data in the stack cache. In this stack cache swap out operation, the data values and tags in N evaluation stack entries of the evaluation stack cache are copied to the previously established main memory location.

Abstract: A plate formed with louvers and a depression to heat engage a hard disk drive motor is attached to such a drive. Heat from the motor is transferred to the plate. The louvers dissipate heat especially if they are in the path of a blower. The plate also protects the user from contact with drive components if touched during installation or removal of the drive while the drive is connected to a computer while electrically energized.

Abstract: An apparatus and method for handling interrupt requests from any of a plurality of interrupters to any of a plurality of interrupt handlers. Each interrupt handler includes an interrupt input request queue for holding a plurality of incoming interrupt requests. A system controller is connected to the interrupters and the interrupt handlers, and includes an input queue coupled to each interrupter for receiving a plurality of interrupt requests. The system controller includes a processor and a memory storing instructions for controlling its operation. The system controller also includes an output queue coupled to each interrupt handler (which in many cases will also be interrupters), and a counter for monitoring the current number, at any given time, of interrupt requests pending in each of the interrupt input queues in the interrupt handlers.

Abstract: Inconsistencies between cache and memory in a memory system operating in a computer are traced and corrected. A cache entry is checked against a counterpart memory entry to trace inconsistencies between the cache entry and the memory entry and to correct the cache entry. A page table entry in memory with a zero mapping mark is checked against a counterpart page entry in a translation lookaside buffer. Inconsistencies between the page table entry with a zero mapping mark and the existence of a counterpart page entry in the translation lookaside buffer is traced. The inconsistency is corrected by deleting the counterpart page entry in the translation lookaside buffer. Address mapping is checked comparing a page entry in the translation lookaside buffer against a counterpart page table entry in the memory. Inconsistencies between the page entry and the page table entry are traced and corrected.

Abstract: A computer processor complex including a hardware processor coupled to a multimedia coprocessor is provided. This computer processor complex is capable of separately processing a stream of non-multimedia instructions in addition to a stream of multimedia instructions such as are used in MPEG audio and video. The computer processor complex includes a visible register set including registers for a program counter and a data pointer. The program counter is used to hold the address in memory where the multimedia instructions are located and the data pointer indicates where the data, corresponding to these multimedia instructions, is located in memory. A hardware processor is coupled to a first bidirectional port on the visible register set and a multimedia coprocessor is coupled to a second bidirectional port on the visible register set. The bidirectional ports allow the hardware processor and the coprocessor to exchange data and status information typically using an interrupt based communication mechanism.

Abstract: A data processor supports the use of multiple memory models by computer programs. At a device external to a data processor, such as a memory controller, memory transactions requests are received from the data processor. Each memory transaction request has associated therewith a memory model selected from a predefined plurality of memory models. In a preferred embodiment, the predefined memory models supported are SSO (strong sequential order), TSO (total store order), PSO (partial store order) and RMO (relaxed memory order). Data representing pending memory transactions are stored in one or more pending transaction buffers and a pending transaction status array. The pending transaction status data includes memory transaction order data that indicates which of the pending memory transactions can be performed before other ones of the pending memory transactions.

Abstract: A circuit for coupling a LIC driver to a IEEE 1149.1 boundary scan implementation includes a logic circuit that converts the data and oe signals of the IEEE 1149.1 specification to test "q.sub.-- up" and "q.sub.-- dn" signals meeting the requirements of the LIC driver. These test "q.sub.-- up" and "q.sub.-- dn" signals are selectively provided to the LIC driver during boundary scan testing of the output driver. In a further refinement, the logic circuit also converts functional q.sub.-- up and q.sub.-- dn signals provided by the circuit under test to the data and oe signals of the IEEE 1149.1 specification. The logic circuit allows the widely used IEEE 1149.1 boundary scan standard to be used with LIC drivers. The resulting compatibility simplifies the testing and use of the LIC drivers, and provides a new boundary scan standard for use with LIC drivers that is compliant with the IEEE 1149.1 standard.

Abstract: An efficient streamlined coherent protocol for a multi-processor multi-cache computing system. Each subsystem includes at least one processor and an associated cache and directory. The subsystems are coupled to a global interconnect via global interfaces. In one embodiment, each global interface includes a request agent (RA), a directory agent (DA) and a slave agent (SA). The RA provides a subsystem with a mechanism for sending read and write request to the DA of another subsystem. The DA is responsible for accessing and updating its home directory. The SA is responsible for responding to requests from the DA of another subsystem. Each subsystem also includes a blocker coupled to a DA and associated with a home directory. All requests for a cache line are screened by the blocker associated with each home directory. Blockers are responsible for blocking new request(s) for a cache line until an outstanding request for that cache line has been serviced.

Abstract: When monitoring a large number of information sources such as pages on the World Wide Web, a user may not have time to normally look at each source at regular intervals. A background process will connect to each source maintained in a database and calculate an estimate of how much the source has changed since the last time a user viewed it. The amount of change is graphically displayed to the user as part of an icon or file listing. The user can thus determine whether the amount of new material justifies connecting to the source.

Abstract: A dynamic logic signal repeater includes a complementary dynamic logic circuit with an input node to receive an input signal and an output node storing a precharge signal. The complementary dynamic logic circuit configuration, transistor sizing, and the use of a precharge driver results in a signal transition trip point for the precharge signal on the output node that is substantially equivalent to the signal transition trip point of a static logic circuit. Thus, the dynamic logic signal repeater has improved noise immunity. An evaluation locking transistor is connected to the complementary dynamic logic circuit and the output node. The evaluation locking transistor prevents the charging of the output node during a dynamic logic evaluation period.