Abstract: An ASIC includes a PLL and digital circuitry to quantize and measure phase and average maximum jitter between a system clock input to the PLL, and a PLL-generated clock signal. The system clock is input to a series-string of delay elements, each contributing a delay of about 1.DELTA.t. Each delay element is associated with a two-input logic element, such as an EX-OR gate or an EX-NOR gate. One input to each two-input logic element is a version of the PLL-generated clock delayed by about (N/2) .DELTA.t. The second input to the first EX-OR is the output from the first delay element, the second input to the first EX-NOR is the output from the second delay element, and so on. Whichever delay element outputs a signal most closely in phase with the delayed PLL-generated clock will have an associated two-input logic element signal with a minimum duty cycle. Each two-input logic element output signal is capacitor integrated, sampled, stored and digitized.

Abstract: An architecture for an information appliance adapted for a specific application supports a variety of appliance personalities, relying on a single core technology. The information appliance comprises an application-optimized hardware platform, including a processor, a display coupled to the processor, an input/output device coupled to an information source and to the processor, a user input device, and working memory coupled to the processor. Non-volatile memory is coupled to the processor and stores appliance operating software and application software. The appliance operating software includes logic executed by the processor, which manages information flow from the information source through the working memory to the display, and the application software includes logic executed by the processor and responsive to the user input to manage selection of information from the information source.

Abstract: A fault-tolerant computer architecture is described wherein the effect of hardware faults is diminished. The architecture employs a main data bus having a plurality of interface slots for interconnecting conventional computer sub-systems. The number and type of sub-systems may vary considerably, however, a central processor sub-system which encompasses the inventive elements of the invention is always included. The central processor sub-system employs a plurality of central processing modules operating in parallel in a substantially synchronized manner. One of the central processing modules operates as a master central processing module, and is the only module capable of reading data from and writing data to the main data bus. The master central processing module is initially chosen arbitrarily from among the central processing modules.

Abstract: A process for generating method invocation instructions for a source-code program expressed in an object-oriented computer programming language is described. The process can be implemented as a compiler or, alternatively, as a combination of one or more utility routines and a compiler. The process first generates a global method selector list (hereinafter referred to as the dispatch table) comprising all of a target program's known method selector strings. Next, a unique constant value identifier is assigned to each unique method selector. Finally, as each source-code method call instruction is parsed during compilation, the compiler uses the method selector's identifier value to generate an instruction to directly load a unique constant value method identifier. In one embodiment, generation of the dispatch table is done a priori to the source-code program's compilation by a utility routine. In an alternative embodiment, the compiler performs these operations directly.

Abstract: A method and apparatus for dynamically reconfiguring a processor involves placing the processor in a first configuration having a first number (m) of strands while the coded instructions comprise instructions from a number (m) threads. The instructions in each of the m threads are executed on one of the m strands using execution resources at least some of which are shared among the m strands. While the coded instructions comprise instructions from a number (n) threads, the processor is placed in a second configuration having a second number (n) of strands. The instruction are executed in each of the n strands using execution resources at least some of which are shared among the n strands.

Abstract: A combined file allocation table file system (CFAT file system) uses two or more FAT file systems with different cluster sizes to form a single user visible FAT file system to reduce disk fragmentation. The FAT file system having the largest cluster size is used to store all of the other small FAT file systems as files with holes. The clusters of the small FAT file systems thus do not occupy disk space until they are allocated. Files containing user data are stored in one or many of the large and small FAT file systems to achieve optimal storage. More clusters are available for storing files with sizes that are smaller than the size of one large cluster. A CFAT file system includes: a large file allocation table for large clusters, a file allocation table extension to provide holes within the CFAT file system, and any number of small file allocation tables providing a variety of small cluster sizes.

Abstract: The method and apparatus for checking and reducing an intermediate result signal arising from a manipulation of data signals without using conditional branches, thereby improving instruction processing in a superscalar pipelined processor or an arithmetic unit that can execute several arithmetic operations concurrently. The data signals are represented as unsigned 8-bit binary values. This requires that the intermediate result signal be stored in a register that is greater than 8-bits wide to allow for the proper checking of an overflow condition. It is presently contemplated that the present invention include using a processor operating under program control with the program having the following operations. The program determines whether the intermediate result signal is in a maximum overflow state or a minimum overflow state. The program sets a first mask signal to have 8 lower bits in an OFF position when the intermediate result signal is in the maximum or minimum overflow state.

Abstract: A "tower"-type computer has a metal frame or chassis enclosed in an ornamental plastic housing. One side of the plastic housing with an attached metal liner is detachable for access to the interior of the chassis. The upper front corner of the chassis is provided with a metallic subframe. The front of the chassis is substantially open in front of this subframe and is formed with ventilation holes below the subframe. A detachable main bezel, divided into three vertically separated sections, covers the front of the chassis. The upper section of the main bezel is substantially open but is provided with ears so that fasteners can connect the ears to the front of the chassis. A peripheral bezel snaps onto this upper section of the main bezel and is provided with three openings which are covered with removable fillers. When a filler is removed, a computer peripheral may be inserted through the peripheral bezel into tracks in a bracket installed in the subframe.

Abstract: Apparatus, methods, systems and computer program products are disclosed that determines what information presented on a computer display screen to a user most interests the user. The invention uses this information to correlate the topics of the displayed information and the user's interest to select additional information for the user. This additional information better matching the user's interest.

Abstract: A method for operating a microprocessor in extracting an arbitrary channel of data from an image of any number of multiple channels with substantially minimized processing cycles per byte. Each channel of an image is preferably sampled with a predetermined data length. Subsequently the microprocessor partitions each of said sampled data according to a partitioning criterion into a plurality of partitioned components and combines a plurality of said partitioned components to form a data variable that is formed only with data components indicative of a selected channel of the image.

Abstract: An apparatus for successive refinement of video frames, and methods of operating the same result in reduced latency for downloading the video frames. The apparatus for transmitting video frames comprises a plurality of video frames encoded to provide a plurality of program modules. A first program module provides a first video frame. A second program module provides an enhancement to the first video frame. A cataloging resource which provides scheduling requests for transmission of the plurality of program modules requests the first program module and the second program module for transmission. An output driver which transmits program modules receives the scheduling requests from the cataloging resource for the first program module and the second program module and selects the first program module and the second program module for transmission to produce a higher quality first video frame.

Abstract: A system and method allow client applications to invoke remote procedures on a server application using any of a plurality of remote procedure mechanisms, by selecting a remote procedure call mechanism at runtime. The system and method uses client and server stubs in the application that include an mechanism-independent canonical specification of each procedure interface. The specification defines the form of the interface and arguments, but not does include conventional mechanism-specific marshalling arguments for marshalling the arguments. The resulting compiled stubs may be used with any remote procedure call engine. Such remote procedure call engines receive the specification of the procedure interface and the arguments passed by the client application to the server, and determine at runtime the particular marshalling routines to use, according to the canonical specification.

Abstract: In a cluster of computer nodes, each node has network interface and at least one processor. Transmission of a multipart message from a first node to a second node is initiated by sending to a network interface of the first node a sequence of PIO store and DMA store commands, each PIO store and DMA store command specifying a respective component of the multipart message to be stored in a respective specified memory mapped location in the second node, the sequence of the PIO store and DMA store commands corresponding to a predefined message component order. The first node's network interface packetizes the sequence of PIO and DMA commands to generate an ordered stream of data transfer packets whose order corresponds to the predefined message component order, and transmits the ordered stream of data transfer packets to the second node so as to store the respective components of the multipart message in their respective specified memory locations in the second node in the predefined message component order.

Abstract: A multiprocessing computer system employs local and global address spaces and Non- Uniform Memory Architecture (NUMA) and Cache-Only Memory Architecture (COMA) access modes. The multiprocessing computer architecture employs a plurality of processing nodes. When a processing node initiates a memory transaction, the node determines whether the address of the memory transaction is a global address or a local physical address. If the address is a global address, a NUMA coherency request is initiated. Alternatively, if the address is a local physical address, a COMA coherency request is initiated. The nodes additionally include local physical address to global address translation units. The local physical address to global address translation units are configured to translate a local physical address to a corresponding global address prior to initiating a COMA coherency request.

Abstract: An intuitive graphical user interface is based upon a geographic map structure, and includes a system for controlling remote external electronic devices. In the defined graphical user interface, each space of the geographic map structure is rendered on a touch screen display as a graphic image of a geographic space. Within each space are colored cartoon-like icons called "objects" which can be selected and manipulated by the user. Certain objects, referred to as portals, transport the user from one space to another space when Selected. Other objects, referred to as buttons, perform associated actions or functions when Selected. The graphical user interface is displayed on a hand-held display device used to control remote devices. Each remote electronic device transmits a user interface program object that defines a graphical user interface to the display device.

Abstract: The present invention relates to a simplified flag control circuitry for use in first in first out (FIFO) memory buffers. The special FIFO memory buffer transfers data between circuits running on different clocks. The present invention delays the initial output of data from the FIFO memory buffer until the memory buffer has received a threshold amount of data. After the threshold quantity of data has been received, the present invention allows output of data from the FIFO.

Abstract: A method and system for providing a fully automated electronic bill processing capability that is integrated with banking institutions and their customers is herein disclosed. The electronic bill payment system includes a community of payors, payees, payor banks, and payee banks that are associated with computing systems-that are interconnected by a computer network. A payor bank receives electronic bills specifying payment requests from one or more payors having an account at the payor bank. The payor bank places a hold on the funds in the payor's account and then generates an electronic check that is transmitted to the payee. The payee receives an electronic check envelope that contains a number of electronic checks that are encrypted and digitally signed by the payor bank. The payee generates an electronic deposit including one or more endorsed electronic checks and a deposit slip. The electronic deposit is encrypted and digitally signed by the payee.

Abstract: An array of DCT transform coefficients are converted to a two-dimensional array of spatial data in a video compression or decompression system. The array of DCT transform coefficients are divided into two groups. A regional IDCT algorithm is applied to all coefficients, both non-zero and zero, of the first group, while IDCT computation is applied to only non-zero coefficients of the second group. The results of the operations are then combined and/or mapped to form the output array of spatial data. In one specific implementation wherein an 8.times.8 array of DCT coefficients are to be transformed, the first region is defined by the first quadrant of coefficients in the 8.times.8 array. A regional IDCT algorithm is applied to both zero and non-zero coefficients in the first quadrant.

Abstract: Method, system and article of manufacture for creating an object oriented component having multiple bidirectional ports for use with an object oriented based applet or application. The component's ports are all first initialized to a predetermined value and thereafter polled to determine if an input has been coupled to any one of the ports. If it has not, polling continues. If an input is present, all of the component's remaining ports are set to output the same type and value as that of the input. Where appropriate, a check is made to determine if a saved state of the component exists. if it does, the component is initialized to the state type and value rather than the predetermined type and value. When the input is removed, the component ports are all reinitialized to the predetermined type and value and polling for a new input commences.