Abstract: A method and apparatus for controlling server activation. In the prior art, there exists a race condition between the shutting down of an old server and the starting up of a new server. Further, rapidly restarting servers, such as daemonic servers, are prone to thrashing behavior. However, an embodiment of the invention avoids this undesired behavior by providing an additional "shutting down" state in the server finite state machine running in the ORB daemon. This additional state allows an old server to complete the necessary shut down procedures prior to the startup of a new server. Also, a process is provided for handling servers that are too slow to shut down or start up. A second additional state is provided in the server finite state machine to handle self started servers.

Abstract: In an out-of-order processor having single-precision floating-point registers aliased into double-precision floating-point registers, a single-precision floating-point arithmetic operation having four possible register dependencies is converted into two microinstructions which are processed normally within the processor. The first microinstruction is coded to perform the arithmetic operation specified by the single-precision instruction using the first and second source registers specified and storing the result in a phantom register. The second microinstruction is coded for merging the contents of the phantom register and the destination register specified. Each microinstruction has at most two possible register dependencies, thereby reducing the total number of register dependencies which the processor is required to track.

Abstract: When a client computer requests data from a disk or similar device at a server computer, the client exports the memory associated with an allocated read buffer by generating and storing one or more incoming MMU (IMMU) entries that map the read buffer to an assigned global address range. The remote data read request, along with the assigned global address range is communicated to the server node. At the server, the request is serviced by performing a memory import operation, in which one or more outgoing MMU (OMMU) entries are generated and stored for mapping the global address range specified in the read request to a corresponding range of local physical addresses. The mapped local physical addresses in the server are not locations in the server's memory. The server then performs a DMA operation for directly transferring the data specified in the request message from the disk to the mapped local physical addresses.

Abstract: A system for screening data packets transmitted between a network to be protected, such as a private network, and another network, such as a public network. The system includes a dedicated computer with multiple (specifically, three) types of network ports: one connected to each of the private and public networks, and one connected to a proxy network that contains a predetermined number of the hosts and services, some of which may mirror a subset of those found on the private network. The proxy network is isolated from the private network, so it cannot be used as a jumping off point for intruders. Packets received at the screen (either into or out of a host in the private network) are filtered based upon their contents, state information and other criteria, including their source and destination, and actions are taken by the screen depending upon the determination of the filtering phase. The packets may be allowed through, with or without alteration of their data, IP (internet protocol) address, etc.

Abstract: A preferred embodiment of the present invention includes a method and apparatus for allocating and using IP addresses in a network of client systems. More specifically, the present invention includes a DHCP server that leases IP addresses to the client systems. The DHCP server works in combination with a secure DHCP relay agent and a secure IP relay agent. Broadcast DHCPREQUEST messages are forwarded to the DHCP server by the secure DHCP relay agent. Before forwarding, the secure DHCP relay agent embeds in each DHCPREQUEST message. The trusted identifier is an unforgeable object specifically associated with the client system sending the DHCPREQUEST message. When the DHCP server receives a DHCPREQUEST message, the DHCP server extracts the trusted identifier. The trusted identifier is then used by the DHCP server to prevent client systems from accessing the IP address leases of other client systems. The DHCP server also counts the number of IP addresses leases assigned to each trusted identifier.

Abstract: A data visualization arrangement facilitates the display of a selected region of a multi-dimensional data object in a selected one of a plurality of display modes. The arrangement comprises a data object store, an interface, an object region retrieval component and a display. The data object store stores the data object, the data object comprising a plurality of data items in a predetermined organization. The interface receives a region identification for identifying a particular region of the object and a display mode identification. The object region retrieval component retrieves data items from a region of the data object as identified by the region identification received by the interface. Finally, the display receives the data items as retrieved by the object region retrieval mechanism and displays them in the display mode as identified by the display mode identification.

Abstract: In one embodiment, the present invention provides a method of selecting a selectable element with a character input device from a list of exically unordered selectable elements on a graphical user interface (GUI). Typically, these selectable elements include hypertext links and GUI buttons on the GUI of computer program executing on a computer system. Each selectable element includes a character portion of data which facilitates selecting the selectable element. The method typically begins the selection process when a user enters one or more characters from a character input device. In response to receiving the characters, the present invention inserts each character into a match string. The match string is then compared with the character portion of each selectable element on the GUI. A selectable element is "armed" when the character portion of a selectable element is found which matches the match string.

Abstract: A single-chip central processing unit (CPU) includes a processing core and a complete cache-coherent I/O system that operates asynchronously with the processing core. An internal communications protocol uses synchronizers and data buffers to transfer information between a clock domain of the processing core and a clock domain of the I/O system. The synchronizers transfer control and handshake signal between clock domains, but the data buffer transfers data without input or output synchronization circuitry for data bits. Throughput for the system is high because the processing unit has direct access to I/O system so that no delays are incurred for complex mechanisms which are commonly employed between a CPU and an external I/O chip-set. Throughput is further increased by holding data from one DMA transfer in the data buffer for use in a subsequent DMA transfer.

Abstract: A system, method, apparatus, and computer program product for avoiding aircraft collisions with stationary obstacles. The aircraft is provided with a simplified uncluttered onboard display of all objects which are in or proximate to the projected path of the aircraft at its particular altitude plus or minus a predetermined increment, such as 100 feet constituting a hazard zone. The display presents the hazards in that zone in geographical relationship to the position and path of the aircraft. In addition to the obstacles in the hazard zone the display may also present topographical features of the underlying terrain. This information is in the form of a muted presentation of a topographical moving map. As the aircraft approaches a hazard in the hazard zone the presentation of the obstacles or hazards within the zone is enhanced to draw increasing attention of the pilot.

Abstract: A computer system includes multiple processing nodes, each of which is divided into subnodes. Transactions from a particular subnode are performed in the order presented by that subnode. Therefore, when a first transaction from the subnode is delayed to allow performance of coherency activity with other processing nodes, subsequent transactions from that subnode are delayed as well. Additionally, coherency activity for the subsequent transactions may be initiated in accordance with a prefetch method assigned to the subsequent transactions. In this manner, the delay associated with the ordering constraints of the system may be concurrently experienced with the delay associated with any coherency activity which may need to be performed in response to the subsequent transactions. In order to respect the ordering constraints imposed by the computer system, a system interface within the processing nodes employs an early completion policy for prefetch operations.

Abstract: According to a presently preferred embodiment of the present invention, a method for processing a incoming signal comprising the steps of selecting a first set of bits of digital information from a first signal, selecting a second set of bits of digital information from a second signal, reading the first set of bits of signal information into a first contiguous memory space to form a first word, and then reading the second set of bits of signal information into a second contiguous memory space to forming a second word, performing a first EXCLUSIVE OR operation on the first word with the second word, performing a first logical AND operation on the first word with a mask, performing a second logical AND operation of said second word with a mask, performing a first addition operation of the results of the first logical AND operation with the results of the second logical AND operation, performing a third logical AND operation on the results of the first EXCLUSIVE OR operation with a mask word, and then performin

Abstract: A processor which includes separate instruction and data caches and which executes instructions according to a new instruction set architecture, efficiently executes old software code by providing the processor with a compatibility circuit which receives old software code instructions from a secondary memory, groups these instructions according the new instruction set architecture and provides these grouped instructions to the instruction cache of the processor. In this processor, the old instruction software code conforms to an old instruction set which is a subset of the new instruction set.

Abstract: A modification to conventional scan chain design is disclosed which can identify whether any connection in the scan chain is shorted to the supply voltage or ground (i.e., shorted to a logical 1 or logical 0) and the precise location of the short. Circuitry in the flip-flops (or other sequential elements) forming the scan chain allows the scan output of each flip-flop to be set or reset by switching a scan enable signal between logic states. If there is a fault in the scan chain where a node is stuck at a logical 1, then resetting the scan outputs of the flip-flops to 0 and clocking the flip-flops will result in a logical 1 being output from the last flip-flop after a number of clock pulses. The number of clock pulses indicates the position of the flip-flop in the scan chain which is associated with the fault. A similar technique detects a stuck-at-0 fault by setting the flip-flops to 1.

Abstract: A n level clock distribution network for a datapath block includes an external buffer that outputs a clock signal and a datapath block having a logic block and a buffer block containing one or more nth-level buffers implemented with predefined modular buffers. The logic block includes one or more predefined areas containing clocked logic elements. The number of clocked logic elements in a predefined area is constrained to be less than or equal to a predetermined maximum number. Each nth-level buffer receives the clock signal outputted by the external buffer and distributes this clock signal to the clocked logic elements within a corresponding predefined area of the logic block. The nth-level buffer driving each predefined area is implemented by selecting one or more buffers from a family of predefined modular buffers appropriate for the number of clocked logic elements in the predefined area.

Abstract: A decode register which receives a first plurality of input lines. If the decode register is not in a scan mode during a given clock cycle, the decode register is configured to convey a decoded output value in response to an input value conveyed on the first plurality of input lines. The decode register also includes a scan decode unit, which receives a second plurality of input lines. When operating in scan mode during a given clock cycle, the decode register is configured to convey a second decoded output value in response to a second input value conveyed on the second plurality of input lines. The second plurality of input lines comprise a scan input line and one or more feedback lines which each correspond to a value on the scan input line during a previous clock cycle. The decode register also includes an encoder which is configured to receive a value indicative of the second decoded output value.

Abstract: Data routing of the present invention is a capability of pre-configuring routes for data traveling through the software or the hardware of a computer system. The routes are set up by a consumer of the data or the destination and are delivered to the producer of the data or the source. The data route may include an identification of the consumer of the data, a minimal list of routines which will perform some preprocessing of the data, a return route, a don't care mask, a set of registered routes and a set of actions. The set of actions can be a set of states to transition or a set of functions to call. In order to determine a data route hit, the incoming data from the producer is AND'ed with the don't care mask, the results of which is then compared with the set of registered routes, i.e. a pattern of bits. If the results are equal, then there is a data route hit. The incoming data from the producer is then passed off to the actions.

Abstract: An apparatus for allowing a RAM array within an SRAM to be tested via scan ATPG is disclosed. A first clocked flip-flop has a data input latched high, a scan-in input latched high, a clock input coupled to a signal source generating a periodic waveform, a scan-enable input coupled to a scan enable signal, and an output. The first flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high. A second clocked flip-flop has a data input coupled to the output of the first flip-flop, a scan-in input latched high, a clock input coupled to the signal source, a scan enable input coupled to the scan enable signal, and an output. The second flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high.

Abstract: Virtual bus stubs, which can be distributed among constituent computers of a computer network, and a central resolver cooperate to simulate a bus which is connected between multiple circuit parts of a simulated circuit. With each simulated cycle of a clock of the bus, the resolver (i) collects data from the virtual bus stubs representing signals driven on the bus by one or more of the circuit parts, (ii) resolves the current simulated state of the bus from the collected data, and (iii) sends data representing the resolved current simulated state of the bus to the virtual bus stubs. As a result, the virtual bus stubs and the resolver collectively accurately simulate the bus connecting the circuit parts. Since each circuit part has access to the simulated state of the bus through a respective virtual bus stub, each circuit part has access to all information regarding the simulated state of simulated circuit which is necessary for the accurate simulation of each circuit part.