Abstract: A method and apparatus to distribute spare cells into a standard cell region of an integrated circuit is described. An initial layout of standard cells is first generated by a place and route tool. Afterwards, the initial layout is processed by a spare cell distribution mechanism that simultaneously processes a directive file. The spare cell distribution mechanism distributes, according to a predefined criteria, a preselected cluster of spare cells within the initial layout of standard cells. This processing results in an optimal distribution of spare standard cells within the standard cell region of the semiconductor. The spare cell distribution mechanism also inserts vertical wire terminators into the standard cell region to promote vertical routing, and thus shorter routing paths. In addition, the spare cell distribution mechanism inserts ground connectors and power connectors in the standard cell region to generate a ground and power paths.

Abstract: A software-based encoder is provided for an end-to-end scalable video delivery system that operates over heterogeneous networks. The encoder utilizes a scalable video compression algorithm based on a Laplacian pyramid decomposition to generate an embedded information stream. The decoder decimates a highest resolution original image, e.g., 640.times.480 pixels, to produce an intermediate 320.times.240 pixel image that is decimated to produce an intermediate 160.times.120 pixel image that is compressed to form an encodable base layer 160.times.120 pixel image. A decompressed base layer image is also up-sampled at step to produce an up-sampled 640.times.480 pixel image that is subtracted from the original 640.times.480 pixel image 200 to yield an error image. At the receiving end, the decoder extracts from the embedded stream different streams at different spatial and temporal resolutions. Because decoding requires only additions and look-ups from a small stored table, decoding occurs in real-time.

Abstract: A single-ended sense amplifier circuit for sensing the state of a bitline in a memory array. The sense amplifier includes an output circuit having an input and an output, the output for indicating a state of the bitline in response to a bitline voltage level. A precharge circuit is coupled to the input for charging the input to a first voltage level when the input is decoupled from the bitline. A discharge circuit is coupled between the bitline and the input. In one embodiment, the discharge circuit includes a field effect transistor coupled as a cascode device for coupling and decoupling the input to the bitline. The discharge circuit couples the input to the bitline when the discharge voltage level exceeds a threshold voltage level of the discharge circuit.

Abstract: A method and an apparatus allowing a system interfaced with a network to continue functioning in a diminished capacity, even when the system is temporarily disconnected from the network. Unmodified applications running on the system which initiate a network-related operation during system isolation are coerced into a fast-fail behavior by fast-fail mechanisms residing in the system's network layer kernel modules.

Abstract: The same hardware is used to implement calculations of the exponents for multiplication, division, and square root in either double or single precision. A multiplexor selects the appropriate bias value necessary for exponent computation for the given instruction type, operand precision, and output precision. A first operand multiplexor selects either the exponent of the first operand in the case of a multiplication or division instruction, and selects zero in the case of a square root instruction, since the square root operation only requires one operand. The second operand multiplexor selects the second exponent in the case of a multiplication instruction, the one's complement of the second exponent in the case of a division instruction, and the second exponent divided by two during a square root operation. Flip-flop registers latch the exponent and incremented exponent when a division or square root operation is pending.

Abstract: A system and method for auditing software packages in a multi-release environment is provided. The audit system reads one or more external files that specify which packaging rules apply to a particular target software package. The audit system also reads package information files of the target software package. The package information files specify the form and content of the target software package. The audit system analyzes the information contained in the package information files to determine whether the target software package conforms with the specified packaging rules. The packaging rules may include rules relating to conflicts between software packages. Under these circumstances, the audit system retrieves information about the software packages against which the target software package is to be compared before performing the audit. The audit system may compare the target software package against another software package, or against a database which contains information about numerous other packages.

Abstract: A method of adapting execution-driven simulators to accept traces is provided. First, a benchmark program is executed to provide a trace file of the executed instructions. Each output instruction of the trace file includes the program counter (PC) and the op code of the instruction executed. In addition for memory access instructions, the trace file includes effective memory addresses, and for decision control transfer instructions, the trace file includes actual branch destinations. Next, the trace file is randomly sampled to produce relatively small segments of contiguous trace instructions. These are then provided to a processor model which processes them concurrently with the benchmark program which is provided in a memory model connected to the processor model. To ensure that the processor design performance is accurately predicted, the trace file effective addresses are used during execution.

Abstract: A compact housing for a workstation-class computer is disclosed. The apparatus includes a structural heat sink with a horizontal base heat sink that includes an interchangeable power source housing and a hard disk drive receptacle. The horizontal base heat sink operates to conduct heat away from the functional elements positioned within the interchangeable power source housing and the hard disk drive receptacle. The structural heat sink also includes a vertical tower heat sink to support functional elements including a power converter. The vertical tower heat sink operates to conduct heat away from the functional elements. The vertical tower heat sink also includes support devices for receiving a detachable pivot display system. The structural heat sink is surrounded by a vented exterior skin that facilitates convective heat transfer from the structural heat sink.

Abstract: A threshold voltage controller circuit for controlling the threshold voltage of complementary metal oxide semiconductor field effect transistors (CMOSFETs) integrated within an integrated circuit includes a test circuit, a clocked voltage comparator and voltage ramp generator. The test circuit simulates a critical signal path within the integrated circuit by receiving a first clock signal and providing in response thereto a corresponding delayed version of such clock signal. The clocked voltage comparator compares the voltage of the delayed clock signal output from the test circuit with a reference voltage and, in response to a second clock signal which is delayed with respect to the first clock signal, asserts a binary output signal high or low if the clock delay introduced by the test circuit is higher or lower, respectively, than desired.

Abstract: A multiplexing non-device specific stream module is provided to an operating system. The multiplexing non-device specific stream module includes a number of upper and lower ports. Each port, lower as well as upper, has a write queue, a read queue, and an associated control and status data area. Additionally, the multiplexing non-device specific stream module further includes a number of service routines, in particular, a splice/unsplice routine, a change ownership routine, and a query ownership routine. Together, these elements cooperate to allow multiplexing of connections to input/output devices with improved performance and flexibility, while maintaining compatibility.

Abstract: A scalable, asynchronous transfer mode ("ATM") interface for generating an ATM cell comprising an addressing element, a memory element and a cell generating element. The addressing element is used to initiate generation of the ATM cell by transmitting one or more memory addresses to the memory element. The memory element, accessible to the addressing element, is used to store at least one datagram corresponding to the memory address(es) and to subsequently output the at least one datagram to the cell generating element. The cell generating element is coupled to the memory element in order to receive at least one datagram and produce the ATM cell. Finally, a controlling element is coupled to the addressing element and the cell generating element in order to control their operations.

Abstract: A computer graphics subsystem is disclosed that renders images on either a high resolution CRT display or a high resolution flat panel display without requiring modifications to existing application programs. The graphics subsystem includes a ramdac circuit that generates a set of video sync signals for a CRT display. The ramdac circuit has an analog video port and a digital pixel output port. The ramdac circuit performs color look-up table and digital to analog conversion functions to drive a high resolution CRT display through the analog video output port. The ramdac circuit uses the digital pixel port to enable the computer graphics subsystem to drive a flat panel display. A color buffer circuit converts the video sync signals into a set of flat panel sync signals for a flat panel display.

Abstract: A method and apparatus is disclosed for interleaving the transfer of pixel data from a dual bank frame buffer to a memory display interface. The interleaved transfer of pixel data to the memory display interface enables upgrade of existing memory display interface designs to higher density VRAM chips in order to increase the capacity of the frame buffer.

Abstract: A system and method for performing conditionally cache allocate operations to a data cache in a computer system. As supervisor mode operations typically do not experience data locality of accesses frequently found in user mode operations, it has been determined that performance benefits can be achieved by inhibiting cache allocate operations during supervisor mode. When a write miss to the cache occurs, the memory management unit checks the state of the processor status register to determine the mode of the processor. If the processor status register indicates that the processor is in supervisor mode, the memory management unit issues a signal to the data cache controller that the data is non-cacheable. When the data cache controller receives a non-cacheable signal, the cache allocate process is not performed. The non-cacheable signal is issued by the memory management unit while the processor is in supervisor mode regardless of the state of the cacheable status bit associated with the memory.

Abstract: A dynamic clocked inverter latch with reduced charge leakage includes a first node biasing circuit with a P-MOSFET and an N-MOSFET totem-pole-coupled between VDD and an output node, and a second node biasing circuit with another N-MOSFET and another P-MOSFET totem-pole-coupled between the output node and VSS. The first P-MOSFET receives an input data signal and the first N-MOSFET receives a clock signal and in accordance therewith together cause the output node to charge to a charged state having a charge voltage associated therewith. The second N-MOSFET also receives the input data signal while the second P-MOSFET receives the inverse of the clock signal and in accordance therewith together cause the output node to discharge to a discharged state having a discharge voltage associated therewith.

Abstract: A client workstation provides a login address as an anonymous ftp (file transfer protocol) request, and a password as a user's e-mail address. A destination server compares the user's e-mail address provided as a password to a list of authorized users' addresses. If the user's e-mail address is located on the list of authorized users' addresses maintained by the destination server, the destination server generates a random number (X), and encrypts the random number in an ASCII representation using encryption techniques provided by the Internet Privacy Enhanced Mail (PEM) procedures. The encrypted random number is stored in a file as the user's anonymous directory. The server further establishes the encrypted random number as one-time password for the user. The client workstation initiates an ftp request to obtain the encrypted PEM random number as a file transfer (ftp) request from the destination server.

Abstract: A high speed line driver circuit that drives an output line based on an input line is disclosed. The high speed line driver circuit uses dynamic precharging of the output lines to speed the transition of the output lines to the proper output voltage level. The high speed line driver circuit precharges the output lines to an equalized voltage level between Vcc and Vss when in a "stand-by" mode. Using an NMOS transistor, the equalized voltage level is Vcc-Vtn where Vtn is the threshold voltage of the NMOS transistor. An edge detection circuit determines when the output lines must be driven. The edge detection circuit normally remains low until a voltage level change on the input line is detected. When a voltage level change occurs, the equalization is turned off and the line driver circuit drives the output lines to the level dictated by the input line.

Abstract: A method for fully supporting floating point multiplication using a combination of partial hardware support and partial software support traps to software when a subnormal operand is encountered and gross underflow cannot be determined without determining the leading zeros in the subnormal mantissa. A simplified hardware multiplier does not require leading zero detection or left or right shifting. The partial hardware support circuit allows single and double precision operands. The hardware multiplier unit only partially supports subnormal operands. If one of the operands is subnormal, the hardware multiplier unit will output zero and a gross underflow signal if the multiplication would result in gross underflow. There is a small minority of operand permutations that are not supported in hardware and thus require a greater time to compute by resorting to software. However, the vast majority of operand permutations gain reduced latency.

Abstract: An asynchronous transfer mode (ATM) segmentation and reassembly (SAR) chip is provided for interfacing a host computer with an ATM system having a physical layer (PHY) chip incorporating, for example, a Unified Test and Operations Physical Interface for ATM (UTOPIA) protocol. The PHY chip is capable of operating at both 155 Mbps and 622 Mbps data transmission rates. The UTOPIA protocol requires a clock which is provided by the SAR chip. In an exemplary embodiment described herein, the SAR chip is configured to accommodate both data transmission rates and to synthesize appropriate clock signals for driving the PHY chip which facilitate the clocking out of data and the sampling of data.