Abstract: A damping circuit is described which includes a phase-and-frequency detector, a charge pump, a voltage-current oscillator and a capacitor. The phase-and-frequency detector generates UP and DOWN signals representative of a difference in phase between a pair of digital input signals. The charge pump varies an amount of charge carried within the capacitor in accordance with the UP and DOWN signals. The voltage controlled oscillator generates an output signal having a frequency controlled by both a voltage provided by the capacitor and by the UP and DOWN signals directly received from the phase-and-frequency detector. No analog damping resistor is required. Rather, the damping circuit is an digital circuit which generates adequate phase and frequency damping without a damping resistor. Damping is achieved which is substantially unaffected by process parameters and operating and ambient parameters. Method embodiments of the invention are also described.

Abstract: A method and apparatus to model the power network of a VLSI circuit is described. The method includes the step of extracting the power network associated with a semiconductor circuit layout. A compacted power network is then derived from the power network. The compacted power network includes a compacted primary resistive network to characterize the electrical resistance of the power trunks within the semiconductor circuit layout. The compacted power network also includes a compacted secondary resistive network to characterize the electrical resistance of power straps that deliver power to transistors within the semiconductor circuit layout. The compacted power network constitutes a network of compaction component values that correspond to functional regions in the semiconductor circuit layout. Each of the compaction component values includes an associated set of spacial compaction values that characterize the total resistance of a functional region.

Abstract: A package for an integrated circuit is described. The package houses an integrated circuit with a signal quality sensitive integrated circuit element, such as a voltage controlled oscillator of a phase-locked loop. A package-mounted storage capacitor is positioned on the package body to generate a precision control signal. A signal path is constructed between the package-mounted storage capacitor and the integrated circuit to route the precision control signal to the integrated circuit. The relatively short signal path from the package-mounted storage capacitor to the integrated circuit has reduced parasitic capacitance, inductance, and resistance to maintain the quality of the precision control signal. To improve signal quality, certain portions of the signal path are electrically isolated with a shielding trace.

Abstract: A reset circuit for a phase detector in a phase-locked loop is described. A first set of input lines receives a first set of latched signals corresponding to a cycle of a reference signal applied to the phase detector of the phase-locked loop. Reset assertion logic is connected to the first set of input lines and executes a predetermined logic function on the first set of latched signals to generate a reset signal that is applied to an output node. The generated reset signal has a cycle duration corresponding to the reference signal cycle duration. Reset de-assertion logic is connected to the first set of input lines and executes a predetermined logic function on the first set of latched signals to de-assert the generated reset signal after a period of time corresponding to the reference signal cycle duration. Similar processing may be performed in relation to a second set of latched signals corresponding to a cycle of a feedback signal applied to the phase detector of the phase-locked loop.

Abstract: A computer graphics system includes a texel value generator capably of generating texel values using a minimal amount of computationally intensive divisions while maintaining a selectable texel accuracy criteria along a scan line. This is accomplished by adaptively selecting divisional points which delineate the scan line segments along each scan line such that the divisional points are as widely spaced as possible without exceeding the selected texel accuracy criteria. Having selected the texel accuracy criteria, such as a texel error bound optimally spaced, divisional points along the scan lines are selected as a function of the selected accuracy criteria. In general, since texture gradients are not evenly distributed over the surface of a given object and texture variations are present between different objects of the image, it is advantageous to adaptively select division points one at a time, skipping as many pixels in between divisional points as the local texture gradient will allow.

Abstract: Methods and apparatus are presented for unobtrusively monitoring processor states and characterizing bottlenecks in an arbitrary customer workload. An instruction queue and an instruction control unit within a pipelined central processor unit (CPU) provide for grouping and issuing multiple instructions per clock cycle for overlapped execution. Additionally, instruction and data caches in operation with integer and floating point function units issue a program counter to the instruction cache, which subsequently supplies instructions to integer and floating point instruction queues. Both integer and floating point unit datapaths comprise fetch, decode, execute, and writeback stages. In the preferred embodiment, ten additional datalines transmitting PIPE signals are routed from the integer and floating point function units to contact pins on an external pin gate array supporting the CPU.

Abstract: A technique is provided for switching circuitry in a manner which allows the circuit to respond quickly to changes in some critical input signals expected to arrive last. In the preferred embodiment the circuits of this invention are provided in triple logic column form. A circuit will typically include at least two logic columns, each having three portions serially coupled between a high and a low potential source. The middle portion of each logic column is connected to the output node and to receive the critical input signal expected to arrive last, or the input signal with the critical timing requirement. The upper and lower portions of each logic column are connected to receive the remaining input signals, that is those input signals not expected to be changing at the time the critical input signal is received. Thus, the state of the upper and lower portions of the logic column can be "set-up" in advance, in readiness for the critical input condition.

Abstract: A charge pump circuit contains a first switch pass gate, a second switch pass gate, a high node regulator, and a low node regulator. The first switch pass gate couples a high node to a charge pump output when an up control signal is active, and the second switch pass gate couples a low node to the charge pump output when a down control signal is active. The high node regulator receives the charge pump output and a source voltage for the charge pump circuit, and generates a high node voltage at the high node such that the high node voltage is regulated to a voltage above a predetermined margin of the charge pump output. The low node regulator is coupled to ground, and receives the charge pump output to generate a low node voltage at the low node that is regulated to a voltage below a predetermined margin of the charge pump output. The charge pump circuit has application for use in a phase lock loop.

Abstract: The present invention provides a multi-level instruction scheduling system for controlling multiple execution pipes of a distributed data flow (DDF) processor. The multi-level scheduling system includes a simple global instruction scheduler and multiple local instruction schedulers corresponding to the number of execution pipes. The global instruction scheduler is responsible for distributing instructions among the execution pipes. Each local instruction scheduler is only responsible for scheduling its share of distributed instructions and matching the reduced number of instructions with the execution units of the corresponding execution pipe when all its source operands are available. Source operands are garnered in one of three ways. First, the local instruction scheduler ensures that locally generated register operand values are stored in a local register buffer and made available quickly to younger instructions distributed to the execution pipe.

Abstract: A method and apparatus for generating a platform-standard object file containing machine-independent abstract code. Source code which defines a procedure is convened into abstract code which makes no assumptions about the platform on which the procedure will be executed. An abstract code platform-standard object file is generated based on the abstract code. The abstract code platform-standard object file includes a list of definitions of any global variables defined in the abstract code, a list of symbol references indicative of any external variables or external procedures referenced in the abstract code, a sequence of machine instructions for calling an execution routine when a client calls the procedure, and the abstract code which defines the procedure. The abstract code is preferably compressed before it is stored in the abstract code platform-standard object file. When a program including the abstract code platform-standard object file is executed, it is dynamically linked to the execution routine.

Abstract: A method and apparatus for the pipelining of data during direct memory accesses. The processor includes an external bus controller, which receives data transmitted across the external bus from an external device, and forwards the data onto the memory bus for transfer to the memory. Similarly, the bus controller receives data to be written to external device from the memory and transfers it across the external bus to the external device. The bus controller includes logic to detect burst transfers and word alignment to determine the minimum number of words that can be transferred across the memory bus while the data transfer from the external device is ongoing. Therefore, instead of waiting for the entire block of data to be received into the processor before transferring it to the memory, portions of the block transferred, for example, two words at a time, are transferred to the memory, while additional data is being received at the processor.

Abstract: A radio transceiver including an antenna for transmitting and receiving radio signals, a reception section for selecting a received carrier signal, a transmission amplifier section for amplifying signals to be broadcast, a mixer, coupled between the reception section and the transmission section, a variable frequency generator for generating local frequencies for the mixer, and a first (synphase) quadrature demodulating channel and a second (square) channel demodulating channel. The mixer includes a first switch, a first double balanced (DB) mixer, intermediate frequency (IF) filter, IF amplifier, power divider, and a second DB mixer. These components are used during both transmission and reception by the radio transceiver.

Abstract: An improved multiprocessor computer system with an improved snarfing cache is disclosed. The multiprocessor system includes a main memory, I/O interface, and a plurality of processor nodes. Each processor node includes a CPU, and a cache. A shared interconnect couples the main memory, I/O interface, and the plurality of processor nodes. The snarfing cache of each processor node snarfs valid data that appears on the shared interconnect, regardless of whether the cache of the processor node has an invalid copy or no copy of the data. The net effect is that each processor node locally caches additional valid data, resulting in an expected improved cache hit rate, reduced processor latency, and fewer transactions on the shared interconnect.

Abstract: A first data processing device (node I) is coupled to a private network which is in turn coupled to the Internet. A second data processing device (node J) is coupled to the same, or to a different network, which is also coupled to the Internet, such that node I communicates to node J using the Internet protocol. Node I is provided with a secret value i, and a public value .varies..sup.i mod p. Node J is provided with a secret value j, and a public value .varies..sup.j mod p. Data packets (referred to as "datagrams") are encrypted using the teachings of the present invention to enhance network security. A source node I obtains a Diffie-Helman (DH) certificate for node J, (either from a local cache, from a directory service, or directly from node J), and obtains node J's public value .varies..sup.j mod p from the DH certificate. Node I then computes the value of .varies..sup.ij mod p, and derives a key K.sub.ij from the value .varies..sup.ij mod p. A transient key K.sub.p is then generated at random, and K.sub.

Abstract: The disclosed invention relates to a computer system, including a crib device and chassis for installing and removing a hard drive to and from the chassis of the system. The drive is securable to the crib device, which has a handle that allows the drive to be carried to and away from the chassis. The crib device and chassis have cams and cam engaging surfaces that cause the crib device and drive to move to effect engagement and disengagement of the electrical connectors of the computer system and drive. Also disclosed is a mounting arrangement for a floppy disk drive and CD-ROM drive.

Abstract: An output display system including an output display; apparatus for controlling the writing of information to the output display; and a double buffered memory including a first bank of video random access memory for furnishing information to the output display, a second bank of video random access memory for furnishing information to the output display, and apparatus for addressing alternate banks of memory as each line of the output display in a frame is written.

Abstract: A system for converting between parallel data and serial data is described. In the system (10), individual bits of the parallel data (12) are latched into individual registers (117). Each register (117) is coupled to a corresponding AND gate (110) which is also connected to receive phased clock signals. The output terminals of the AND gates (110) are connected to an OR gate (115). Using the system, with appropriately phased clocks, the parallel data is converted into serial data.

Abstract: The present invention includes a connector that mates to the software-controllable parallel port output connector on a host device, a passive logic unit, and, preferably, a host-executable software program. The connector provides four loop-back connections: the AUTOFEED and FAULT pins are looped-together, as are the STROBE and BUSY pins, the INITIALIZE and SELECT pins, and the SELECT IN and PRINTER ERROR pins. The eight pins for data line output signals are input to the passive logic, which logic logically "OR's" the data line signals. The logical-OR output signal is fed back to the ACKNOWLEDGE pin of the connector, and signal ground pins on the connector are connected to ground. During testing, the connector and passive logic unit are connected to the host output parallel port, which typically is a 1284-compliant or other Centronics parallel-compatible port.

Abstract: A translation look aside buffer including virtual page table pointer tags provides a system and method for accessing page table entries in page memory of the translation look aside buffer with decrease latencies caused by accesses to increasing levels of page tables during a table walk of the page table. Virtual tags identifying page table pointers at a predetermined level of the page table higher than the initial context level of the page table are included in the tag memory of the translation look aside buffer. These virtual tags provide a pointer which directly points to the page table pointer at that predetermined level of the page table. Therefore, if a TLB miss occurs wherein a tag for a page table entry corresponding to the virtual address is not found, a comparison is performed to determined if a corresponding virtual tag PTP is located in the tag memory.

Abstract: An apparatus and method to dynamically partition a set-associative memory device is described. The apparatus includes a set identification device to specify a group of set-associative data blocks in a cache memory or translation-lookaside buffer. A block replacement logic circuit is used to identify replaceable blocks within the set-associative data blocks that can store new information. The block replacement logic circuit is also used to identify un-replaceable blocks within the set-associative data blocks that cannot store new information. The block replacement logic circuit only writes new information to the replaceable blocks of the set-associative data blocks. The block replacement logic circuit can be implemented using a block replacement mask to identify within the set-associative data blocks the replaceable blocks and the un-replaceable blocks.