Abstract: A storage cell includes a first bit line, a storage circuit, and a pass transistor. The storage circuit has a first storage node for holding a logic state indicative of a logic value. The pass transistor is coupled to the first bit line and the first storage node for establishing a conduction path therebetween. The pass transistor receives a bias voltage to switch the pass transistor into a substantially nonconducting state when the storage cell is not being accessed. The reverse bias on the first transistor substantially reduces the leakage current through the pass transistor.

Abstract: A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective master cache index. Each master cache index has a set of master cache tags (Etags), including one cache tag for each data block stored by the cache memory. Each data processor includes a master interface having master classes for sending memory transaction requests to the system controller. The system controller includes memory transaction request logic for processing each memory transaction request by a data processor. The system controller maintains a duplicate cache index having a set of duplicate cache tags (Dtags) for each data processor.

Abstract: A repository, a loader, a model generator, a constraint generator, and a number of timing analysis tools, are provided for managing timing requirement specifications and measurements, and generating timing models and constraints of a VLSI circuit. The repository stores the timing specifications and measurements for each pin instances and each flow through arc instances. Timing specifications and measurements are identified by their classes including at least one current specification class and at least one measurement class for one timing analysis tool. Additionally, the repository stores a number of characteristics for each pin instance, the pin compositions of each net, and the hierarchical relationship of the functional block instances. The loader loads the various information into the repository. The timing model generator generates the timing models for the various functional blocks, using the stored information in the repository.

Abstract: The invention provides a method and apparatus for dynamic patching for run-time error checking. With the present invention, a program to be error checked is read into memory where a debugging module resides. Such in-memory copy of the program is scanned for load objects. The load objects comprise libraries used by the program being error checked, as well as the main routines of such program. Next, a list of patch sites in the load objects is created and these patch sites corresponds to address locations in the load objects to be patched. Address space is then allocated for sections of the patch area where calls to real checking code resides. Finally, patches are written out to the in-memory copy of the program to be error checked. The original instruction in a patch site is replaced with branch to patch area instruction and the original instruction displaced is stored in the patch site's corresponding section of the patch area.

Abstract: A memory cell is disclosed. The memory cell operating within a power supply range that induces the pass transistor(s) of the memory cell to be reversed biased when the memory cell is not being accessed. The memory cell includes a storage element capable of storing either a first data value or a second data value, a pass transistor, coupled to the storage element, and a power supply generator is coupled to the storage element. The power supply generator is configured to generate supply level voltages for the storage element so as to induce the pass transistor into a substantially reverse-biased state when the storage element is not being accessed, regardless of whether the storage element is storing the first data value or a second data value.

Abstract: An extensible set of auxiliary services for objects in an object-oriented system. Every object in an object-oriented system is implemented by an associated object manager. Each object manager in the present invention has an associated object manager identifier that identifies the object manager. Each object manager in the system can optionally provide various auxiliary services for objects that the object manager implements. These auxiliary services are objects implemented by the object manager itself, or by another object manager. For a particular type of auxiliary service, different object managers may provide different auxiliary services. For example, two object managers may provide two different freeze-melt services. For each type of auxiliary service type, there is a well-known context in which auxiliary services of that type are associated with names. For each type of auxiliary service, there is also a well-known function that transforms an object manager identifier into a name.

Abstract: A frame buffer memory device controller that schedules and dispatches operations to frame buffer memory devices is disclosed. The frame buffer memory device controller schedules and dispatches cache control operations to reduce timing overheads caused by cache prefetch operations, and operations to write back dirty cache lines and clear cache lines in the frame buffer memory devices. The frame buffer memory device controller also schedules and dispatches control operations to reduce timing overheads caused by video refresh operations from the frame buffer memory devices video output ports.

Abstract: There is disclosed a cover for protecting the leads extending between a silicon chip device and an associated printed circuit board and their electrical connections with the board. The cover is formed out of clear plastic allowing inspection of the chip device and has several legs for securing and maintaining the cover on the board and has openings that allow for cooling of the chip device.

Abstract: In a communication network having a set of hosts and switch based label swapping communication nodes, each node has a control processor that is also a host that sends and receives messages via the switching apparatus in its associated node. Each node's control processor also includes a virtual connection (VC) traversal procedure that implements the methodology of the present invention. The control processor of any node along an established connection can initiate the transmission of a VC traversal message to the control processors of all the nodes along the connection. The VC traversal message is transmitted as one or more ATM cells, where each cell includes a standard ATM header for routing the cell to a neighboring node's control processor, as well as a VC traversal header in the body of the cell that identifies the connection being traversed.

Abstract: A secure naming model for objects in an object-oriented system, wherein names are bound to objects within context objects. The context objects are implemented by name servers, and clients request that a context object "resolve" the name for the object. The name server that implements the context returns a duplicate of the desired object. If a name resolution involves more than one name server, an assurance of security is provided by the first name server to the second name server.

Abstract: An arrangement for assuring the compatibility of versions of software produced for a particular computer hardware architecture including a hardware version register, apparatus for providing an indication of a version of hardware being utilized to operate a particular version of software, a software version register, apparatus for providing an indication of a version of software being run on the particular version of hardware, apparatus for comparing the version of hardware and the version software, and apparatus responsive to the results of the comparison for setting defaults and enabling circuitry in the hardware so that the version of software runs correctly on the version of hardware.

Abstract: A differential to single ended sense amplifier utilizes a minimum number of stages to convert a differential input signal received from complementary bit lines to a single ended output signal indicative of the state of the data stored in a selected memory cell connected to the complementary bit lines. The circuit is constructed to operate with low voltage swings, thereby increasing the switching speed and thus the sense speed. The sense amplifier includes power down capabilities and the ability to tristate its output terminal while in a standby mode of operation during which it is capable of reading the logic level of an input signal. In one embodiment, the output signal is latched using a simple register when the output stage goes tristated, to continue to provide a valid output signal while a subsequent sense operation is performed.

Abstract: The present invention provides an elegant and simple way to provide mechanisms for invocation of objects by client applications and for argument passing between client applications and object implementations, without the client application or the operating system knowing the details of how these mechanisms work. Moreover, these mechanisms functions in a distributed computer environment with similar ease and efficiency, where client applications may be on one computer node and object implementations on another.The invention includes a new type of object, termed a "spring object," which includes a method table, a subcontract mechanism and a data structure which represents the subcontract's local private state.

Abstract: A combination of a plastic part and metal part functions as a fastener to attach a panel to the flange of a portion of a chassis for electronic equipment or the like. The panel is formed with a counterbored hole and has an arcuate groove outside the counterbore on the outside of the panel and angularly spaced dimples on the underside. The fastener is a peripherally flanged hollow cylindrical member fitting into the hole and counterbore. It has a partially closed bottom and opposed openings in the cylindrical walls. A detent slants upward-outward from the bottom through one of the openings. A metal clip attaches to the cap, having an inverted U-shape having a web and two depending sides which fit through the openings. The top has a shoulder which locks outside the detent to hold the parts assembled and has a locking extension beyond the shoulder.

Abstract: A method for the stateless propagation of rename's between hierarchial file name spaces is provided. Under the method any standard rename command may be used on a filename located in a local file system name space (FSNS). Thereafter, when a file is renamed, that rename may be propagated through the use of three steps. First, when files have been renamed in either the local, remote or both FSNS, the filenames in the local FSNS must be matched with the corresponding file names in the remote FSNS. Then, after a match has been made, the current rename state is determined to see if the file was renamed in either, both or neither FSNS, or to see of the filename describes a new file not found in the other FSNS. Finally, after the name history for each file in both the local and remote FSNS's are updated, a propagation can occur which updates any changed file names in the remote FSNS, and also updates the entries in the remote FSNS name table and the local FSNS name table to reflect any such changes.

Abstract: A pseudo-random test system which generates the text for a sequence of assembly language instructions by intermixing text instructions generated by pre-programmed operations from at least two test generators is provided. The test generators are executed to program operations into a test interpreter which mixes the operations and outputs text for a pseudo-random sequence of assembly language instructions for execution on a processor. In addition to mixing text instructions generated by pre-programmed operations, the system randomly allocates internal registers and provides self-checking constructs used to compare the processor's results with expected results.

Abstract: A master bus interconnecting multiple masters is coupled via any number of intervening buses to a slave bus interconnecting multiple slaves and masters. A lock arbiter signal is passed to each successive bus-to-bus interface concurrent with an instruction issued by a master accessing a slave on a remote bus. Address, control, data, and lock arbiter signals are buffered in successive intervening bus-to-bus interfaces including the bus-to-bus interface to the slave bus. The lock arbiter signal when received by the slave bus-to-bus interface will set a lock arbiter register within bus slave bus-to-bus interface. Setting the lock arbiter register once a target slave has been accessed prevents any other master operating on the remote bus from using the remote bus or connecting to the remote bus-to-bus interface.

Abstract: A counterflow computing pipeline including a series of similar stages is disclosed. In the basic form of the pipeline, the stages are arranged in a linear fashion and each stage in the pipeline communicates with its two adjacent stages. The flow of data elements in the pipeline is bi-directional. A first data stream of data elements flows in a first direction from stage to stage in the pipeline. A second data stream of data elements flows from stage to stage in the pipeline in a second direction counter to the first direction. Circuitry at each stage is provided so that every data element flowing in the first direction meets each and every data element that it passes flowing in the second direction. According to various embodiments of the invention, when two data elements meet at a stage, circuitry may be provided to compare the data elements, copy data from one data element to the other, or otherwise, cause the data elements to interact.

Abstract: Lists of candidate faults within an integrated circuit are generated, for the purpose of fault diagnosis, by performing a partial intersection of fault lists output from a full-scan test such as a JTAG test. The fault lists represent all candidate faults which may be responsible for producing a mismatched bit between an output test vector and an expected test vector provided by the full-scan test. The partial intersection is performed by first determining the number of occurrences of each candidate fault within all lists associated with each mismatched bit. Then, only faults which occur at least a pre-selected number of times are selected. In this manner, lists of candidate faulty gates are generated based on the relative degree of intersection between fault sets.

Abstract: An improved approach for breaking the bit lines of a semiconductor memory device into small pieces, referred to herein as Embedded Access Trees (EATs), is introduced. Embedded Access Trees enjoy the principal advantage of the banked approach by dividing long bit lines into several smaller bit lines to decrease the effective load which a selected cell must drive. However, EATs avoid most of the limitations of the banked approach, e.g., increased size, power and complexity. In a preferred embodiment of the invention, EATs are embedded into the existing full array and do not require additional peripheral decoders, MUXes or complex and costly global routing. For a given processing technology, the present invention permits a full memory array to be subdivided into more subarrays than the banked approach, with corresponding performance improvements.