Abstract: In a processor, an instruction unit that issues a plurality of instructions is coupled to a mapping unit. Each instruction contains at least one "virtual" address corresponding to a user-addressable register as defined by an instruction set architecture. A register file having a number of physical register addresses in excess of the user addressable virtual register address is also coupled to the mapping unit. The mapping unit receives instructions from the instruction unit and generates a map value for each virtual register address. The mapping unit also maintains a status value for each physical register address. Maintaining the status value provides for out-of-order completion and in-order retirement. A new mapping is generated each time a virtual register address is used as a destination register address of an instruction. This insures that no physical register address will be overwritten before all older instructions have been resolved.

Abstract: The disclosure relates to a latching mechanism for securing an enclosure case of a computer system to a rack. The rack has two pairs of spaced apart posts, each having attachment locations for supporting two cooperative oppositely facing bracket members. The bracket members include platforms for supporting the bottom of the case, such as a case for a CPU. Each member has supports for rotatably receiving a torsion shaft of a latch. Each shaft is formed with two spaced apart arms having outer portions that engage the upper corners of the opposite sides of the case at two locations on each side. The arms of each shaft are angularly displaced relative to each other along the shaft so that one arm is caused to engage the case before the other arm, and in effecting the holding contact of the arms a torque is placed on the shaft, which remains as a positive force latching the case to the bracket and hence to the rack.

Abstract: A module is sandwiched between an underlying member and a superimposed enclosure. The underlying member may be a base or another enclosure. The module is constructed so that it can be secured to the underlying member. The superimposed member has feet formed with horizontal grooves which fit into pockets in corners of the module. A slide is horizontally movable in the module between retracted position and an operative position. In the operative position edges of the slide engage in the grooves in the feet to lock the superimposed enclosure to the module and thereby to the underlying member. The slide may be detachably secured in operative position.

Abstract: A double buffered output display system including a first frame buffer, a second frame buffer, a multiplexor for furnishing data to an output display from one of the first or the second frame buffers, apparatus for storing a signal indicating that the multiplexor is to select a different frame buffer to furnishing data to an output display, and apparatus for furnishing the stored signal to the multiplexor only at the completion of a frame on a display and before a new frame commences.

Abstract: An integrated circuit package is disclosed. The integrated circuit package includes a substrate having a cavity formed therein for enclosing an integrated circuit. The integrated circuit package also includes a carrier for holding the integrated circuit. The carrier is positioned within the cavity of the substrate. A thermally reactive connector is coupled to the carrier. The thermally reactive connector is for selectively coupling the carrier to the substrate when a temperature of the thermally reactive connector is above a first temperature such that the carrier is held in position within the opening. The thermally reactive connector is also for decoupling the carrier from the substrate when the carrier temperature is at the first temperature. In this manner, the number of thermal paths between the integrated circuit and the substrate of the integrated circuit is reduced.

Abstract: A frame buffer dynamic random access memory (FBRAM) is disclosed that enables accelerated rendering of Z-buffered graphics primitives. The FBRAM converts read-modify-write transactions such as Z-buffer compare and RBG alpha blending into a write only operation. The FBRAM also implements two levels of internal pixel caches, and a four-way interleaved frame buffer.

Abstract: Deadlock detection and masking systems are incorporated into a bus coupler intercoupling at least two buses, wherein at least one master is coupled to each bus and at least one slave is coupled to at least one of the buses. The bus coupler also includes an arbiter coupled to the buses to determine which master may control each bus. The deadlock detection system detects a potential arbitration deadlock condition between two master devices seeking control of a bus and access to a slave. Once a potential arbitration deadlock is detected, the masking system is activated to prohibit the second master from gaining control of the second bus for a random period of time. The random time delay acts as a mask to provide the first master device an opportunity to reaccess the slave device and avoid the deadlock situation. By providing a random masking period complementary, synchronized arbitration deadlocks are avoided.

Abstract: The multiple-input OR-gate includes a set of pull down transistors connected in parallel to a common signal line. A pair of first and second inverters are connected along the common signal line between the input pull down transistors and an output. A feedback element connects an output of the second inverter to an input of the first inverter. The inverters are configured to maintain the input of the first inverter at a first intermediate voltage level of V.sub.cc -2 Vt. Input signals received by the input transistors cause the voltage on the signal line to be pulled from the first intermediate level toward Vss. The first inverter responds by generating an output signal which swings from a low voltage of V.sub.ss towards a second intermediate level of V.sub.cc -0.7 Vt. The second inverter responds by generating an output signal which swings between the high level of V.sub.cc and a low level of V.sub.ss.

Abstract: A latch-up pulse generator system includes a latch-up pulse generator coupled to first and second power supplies, for outputting JEDEC-standardized first and second output pulse trains. The generator includes a master clock, digital frequency dividers, and digitally controlled delay circuitry for outputting the two pulse trains. The first pulse train is a square-wave signal with a repetition rate of about two seconds. The second pulse train has a pulse width that is digitally controllable between about 0.2 .mu.s and 5 .mu.s. The delay between the fall-time of the second pulse train and the fall-time of the first pulse train is variably controlled between about 1 .mu.s and one second in 1 .mu.s steps. The amplitude and current output of each pulse train may range from 0 to perhaps 15 VDC at a current level of about 5 A. For power pin latch-up testing, the two pulse trains are combined to produce a composite pulse train. Signal and/or power pins of a CMOS device under test may be analyzed.

Abstract: A circuit for evaluating logic inputs responsive to a reference clock, which circuit includes a first clock terminal for coupling with a first clock, the first clock being delayed from the reference clock by a first frequency dependent delay period. The circuit includes a second clock terminal for coupling with a second clock, the second clock being delayed from the reference clock by a second frequency dependent delay period. The inventive circuit further includes a first circuit stage, which includes a pulse generation circuit coupled to both the first clock terminal and the second clock terminal. In one embodiment, the first circuit stage further includes an output terminal, an evaluation device coupled to the output terminal and the pulse generation circuit. The first circuit stage also includes a precharge device coupled to the output terminal, a third clock terminal, and a first logic level, the third clock being delayed from the reference clock by a third frequency dependent delay period.

Abstract: A redundant blower unit is installed in a rack above another unit containing heat-emitting electrical elements (such as CPU cards) in order to draw air through the underlying unit and out to atmosphere. Four blowers in the blower unit draw air from a plenum, each blower discharging into an individual exhaust duct leading to the exterior. Two blowers are positioned at a first tier relative to the bottom of the plenum and the other two at a second tier higher than the first tier. If one blower fails, its exhaust duct may malfunction as an air inlet, in which case the incoming air is mixed with exhaust air and discharged through the other blower in the same tier as the failed blower. Thus the efficiency of the two blowers in the other tier is not impeded.

Abstract: An input device emulator comprises an interpreter and a router is provided to a windowed environment. The interpreter reads and interprets commands of a first application program and generates simulated input device messages. The router routes the simulated input device messages to a window sever, which in turn translates the simulated input device messages into simulated input events and forwards them to a second application program. Additionally, the router also routes real input and output device messages between the I/O devices and the window server. At initialization, instances of the router are pushed onto appropriate locations in the various input/output streams of the operating system. Thus, input events are simulated with increased reliability, and without requiring modification to the window server.

Abstract: A computer system for generating a summary of test coverage for a hardware description. The hardware description corresponds to a finite state machine (FSM). This embodiment requires at least one test vector. The computer system comprises a memory and a processor. The memory is for storing the hardware description and the test vector. The processor, coupled to the memory, uses the hardware description and generates state information corresponding to the FSM. The processor, using the state information, further generates a first description. The first description includes a description for monitoring states and signals in the hardware description. The processor, using the test vector, the hardware description and the first description, further generates the test coverage summary.

Abstract: A sector cache tag structure for a computer system with a cache memory and a maximum amount of system memory is disclosed. Upon initial power-up of the computer system, the amount of system memory installed in the computer system is determined. A minimum number of sub-blocks for the cache memory is selected such that when less than the maximum amount of system memory is installed, fewer sub-blocks are selected for each block in the cache memory. Based on the optimal number of sub-blocks selected for the amount of installed memory, a plurality of cache tags, block valid bits and sub-block valid bits are stored. The number of cache tags and block valid bits is equivalent to the number of blocks in the cache memory, and the number of sub-block valid bits is equal to the number of sub-blocks. The cache tags are stored in a cache tag random access memory (RAM).

Abstract: A frame buffer including an array of memory cells for storing data indicating pixels to be displayed on the output display, row addressing decoding apparatus and column address decoding apparatus for selecting memory cells positioned in the array, apparatus for transferring a row address to the row addressing decoding apparatus upon the assertion of a row address strobe signal, apparatus for transferring a column address to the column address decoding apparatus for decoding upon the assertion of a first column address strobe signal, apparatus for latching a column address and any data necessary to complete the access during the first column address strobe signal, apparatus for accessing the particular column the address of which has been latched during the latching of a next subsequent address of a column to be accessed along with any data necessary to complete the next access during the next subsequent column address strobe signal following the first column address strobe signal.

Abstract: A system and method for testing and evaluating a display device and its associated display drive circuitry through computer generated graphic test patterns which are dynamically alterable. The system comprises a display device for displaying the test patterns, a computer for generating the test patterns which typically are dynamically alterable and a communication line for coupling the computer and the display device together so that the computer can transmit information forming the test patterns to the display device. The test patterns are monitored visually to detect video artifacts. Alternatively, monitoring may be performed by measuring devices such as signal analyzing devices or optical testing devices.The method for evaluating and detecting video artifacts of a display device and its associated display drive circuitry is performed through at least three steps.

Abstract: An integrated circuit package is disclosed. The integrated circuit package includes a substrate having a cavity formed therein for enclosing an integrated circuit. The integrated circuit package also includes a carrier for holding the integrated circuit. The carrier is positioned within the cavity of the substrate. A thermally reactive connector is coupled to the carrier. The thermally reactive connector is for selectively coupling the carrier to the substrate when a temperature of the thermally reactive connector is above a first temperature such that the carrier is held in position within the opening. The thermally reactive connector is also for decoupling the carrier from the substrate when the carrier temperature is at the first temperature. In this manner, the number of thermal paths between the integrated circuit and the substrate of the integrated circuit is reduced.

Abstract: An apparatus and method for controlling the initialization of shifting circuitry which provides column redundancy for multiple banks of cache memory on-board a microprocessor. Upon sensing deassertion of a reset signal, a master controller supplies non-overlapping two phase clock signals to one bank controller for each bank of the cache memory. Each bank has a set of fuses which supply a bank shift location to the bank controller indicating the location of a bad column in the bank. The master controller also activates a pre-loadable counter which provides each bank controller with a signal which counts down to zero from half the maximum number of columns in a bank. Each bank controller then provides the shifting signals necessary to initialize the shifting circuitry for its bank. In this way, defective columns located in different positions in each bank can be replaced by redundant paths, thereby repairing the cache and increasing the manufacturing yield of microprocessors with an on-board cache memory.

Abstract: The system of the present invention provides for the verification and testing of electrical circuits and the generation of the information necessary to interface with computer aided testing equipment to physically test the fabricated circuits. The verification of the circuit is divided into two portions, functional verification and timing verification. Information generated during the verification process using the separate functional and timing verification information are then combined into a core structure from which test vectors are generated in a format compatible with a circuit testing apparatus which physically tests the fabricated circuit. In this format, unit delays previously employed to perform the timing tests are adjusted according to the timing specifications of the components to comply with the setup and hold times specified. Using this process, the test vectors required by the physical test apparatus to physically test a fabricated circuit are generated.

Abstract: A process and apparatus are disclosed wherein a local data terminal equipment ("DTE" ) node which has the capability of using RFC 1144 TCP/IP header compression/decompression, can negotiate with an unknown remote DTE located at another end of a TCP/IP/X.25 network link, to determine if the remote DTE also supports RFC 1144 TCP/IP header compression/decompression. The disclosed apparatus and process permits a user (such as a systems administrator, for example) to instruct the local DTE that a remote DTE is known to support TCP/IP header compression/decompression whereby the local DTE sets its routing information to record this information. Alternatively, the local DTE can automatically query an unknown remote DTE to determine if it supports TCP/IP header compression/decompression and set its routing information accordingly.