Abstract: A data latch with reduced data signal leakage includes a latch circuit and a clock buffer circuit which provides a differential clock signal to the input transmission gate of the latch circuit. The clock buffer circuit is biased between upper and lower supply voltage potentials which are higher and lower, respectively, than those between which the latch circuit is biased. This causes the differential clock signal to be overdriven with respect to the incoming data signal which is latched by the latch circuit. As a result, the input transmission gate of the latch circuit is reverse-biased during the inactive state of the differential clock signal, thereby isolating the storage node within the latch circuit and preventing signal leakage therefrom.

Abstract: A circuit for reducing current leakage in a logic circuit such as a write driver circuit in a memory array is disclosed. The current leakage reducing circuit includes a data line configured to be set to a predetermined voltage, a data drive circuit, and an enable circuit. The enable circuit is coupled to the data line and the data drive circuit, and is configured to enable the data line to accept a data value from the data drive circuit. The invention also includes a current leakage prevention circuit, coupled to the enable circuit, and configured to substantially reduce leakage from the data line through the enable circuit when the enable circuit is not enabled.

Abstract: The present invention provides an elegant and simple way to provide mechanisms for invocation of objects by client applications and for argument passing between client applications and object implementations, without the client application or the operating system knowing the details of how these mechanisms work. Moreover, these mechanisms functions in a distributed computer environment with similar ease and efficiency, where client applications may be on one computer node and object implementations on another. The invention includes a new type of object, termed a "spring object," which includes a method table, a subcontract mechanism and a data structure which represents the subcontract's local private state. This application is directed to a Shared Memory subcontract whereby a client and a server can share a memory region for argument and results passing in certain circumstances without the intervention of the kernel and with no restrictions on the type or complexity of the arguments being exchanged.

Abstract: Methods and apparatus for operating a power sequencer/controller system are disclosed. In a typical operation, an AC power sequencer/controller of the present invention senses the current through a first outlet connected to a first load, and when the current through the first outlet exceeds a first threshold voltage, indicating that the first load is turned on, the AC power sequencer/controller provides power to a second outlet so that a second load connected to the second outlet can be turned on.

Abstract: In this disclosure an architecture for extensible file systems is described. Also disclosed is an implementation of the architecture. The architecture enables the extension of file system functionality by stacking (or composing) new file systems (layers) on top of existing file systems. The implementor of a new layer has the option of keeping the files exported by the new layer coherent with files of the underlying layer, as well as the option of sharing the same cached memory with the files of the underlying layer. A flexible framework is also disclosed for arranging the file systems' name spaces. Composing of new layers on top of existing ones can be done statically (at compile/configuration time) or dynamically (at boot/run time). In addition, the file system layers can reside in the same address space or in different address spaces, and be implemented on a local computer node or on a remote computer node.

Abstract: An interrupt steering control mechanism includes an interrupt target register storing a code identifying a particular interrupt target processor to receive undirected interrupts within a multiple processor computer system. The computer operating system assigns a particular processor to be a current interrupt target by writing the identifying processor code in to the interrupt target register. A system interrupt pending register permits any processor to ascertain whether an interrupt source has requested service. Each interrupt service request is assigned an interrupt priority determining when the particular processor will service the interrupt in relation to other interrupts pending for that processor. An interrupt target mask register permits the current interrupt target processor to delay service of the interrupt request until some later time, and any processor may assert ownership of the current interrupt target.

Abstract: An improved serial communications circuit, which includes support for Infra Red communications over a number of incompatible IR protocols is provided. To improve serial throughput, and reduce the overhead required of a Central Processing Unit, separate Transmit and Receive FIFO's are provided to buffer incoming and outgoing serial data. These FIFO's are controlled by a state machine which can adjust interrupt requests to the CPU based on the contents of the FIFO's and the time elapsed between interrupt service requests. In addition an improved multi-mode Infra Red modulation and demodulation system is provided which may support, alongside standard hard wired serial communications, wireless IR communications with personal information managers, laptop and palmtop computers, and other personal and professional electronic equipment which may employ an IR remote control.

Abstract: A battery system includes intelligence to allow the battery system to control various aspects of the charging and discharging of the battery, as well as to constantly monitor the battery voltage, temperature, current charge/discharge rate, and remaining capacity of the battery. The intelligent battery system is capable of being charged from a simple voltage supply, with all aspects of charge/discharge rate control and monitoring being accomplished as a function of the intelligent battery system itself, rather than as part of an external charging circuit, or an external electronic device to be powered by the intelligent battery system. This alleviates the need for external systems to include such circuitry and control elements and allows, if desired, a variety of intelligent battery systems to be developed for use with a given electronic system or family of electronic systems, with each battery being able to control its own charge/discharge rates and monitoring functions.

Abstract: A logic and memory circuit with reduced input-to-output signal propagation delay includes signal processor and memory elements connected in parallel for performing "memory work" simultaneously with "logical work" and/or "electrical work." Incorporated within a flip-flop having master and slave latches which perform the memory work (i.e. data storage) on the input and output logic signals, respectively, is a signal processor which processes one or more input signals to provide an output signal. Where memory work and electrical work are to be performed simultaneously, the signal processor includes a serial group of circuits having successively larger transistors for buffering an input signal to provide the output signal simultaneously with the storage of the input and output signals by the master and slave latches, respectively. Where memory work and logical work are to be performed simultaneously, the signal processor includes a logic function circuit (e.g.

Abstract: A method and apparatus for automatically generating device names in a computer system, wherein device names are generated to reflect the physical realities of system configuration. An existing device driver interface is employed, wherein a parent device driver's bus.sub.-- ctl function, along with a child device driver's probe and attach routines, are used to generate device names.

Abstract: A bi-directional ring bus structure is formed on an integrated circuit from a conductive bus and M X:1 multiplexer modules (where M is an integer .gtoreq.2), coupled in a point-to-point configuration. Each module is associated with an input/output port that can communicate with the bus. Each module has an output port (Dout), and arbitration ("ARB") port, and X input ports ("LOCALout", "Din1", "Din2", . . . "Din[X-1]"). The Dout output port of an M.sub.i module is coupled, via a portion of conductive bus, to [X-1] input ports on an adjacent D.sub.i+1 module. Thus, module M.sub.0 's Dout.sub.0 output port is coupled to [X-1] input ports on module M.sub.1, module M.sub.1 's Dout.sub.1 port is coupled to [X-1] input ports of module M.sub.2, and so forth. The modules are X:1 in that the output port of each module is coupled to a chosen one of that module's X INPUT ports, as determined by the state of an arbitration select signal (ARB) coupled to the module's arbitration port.

Abstract: A boot device, a local or remote install media, and a local or remote storage device are provided to a computer system. The boot device comprises an install media locator and starter module. The local or remote install media comprises an install set up and control module and an install module. The local or remote storage device comprises a defaulted or a customized collection of installation files. The defaulted/customized collection of install files comprise a classification rules file, a number of pre-install class class script files, a number of install class parameter files, and a number of post-install class script files. Together, these elements cooperate to automatically install software products on the computer system, and configure the operating environment of the computer system.

Abstract: A touch screen power control function in a computer system, wherein a touch screen input device is employed to control power modes for the computer system. A touch screen controller senses a touch input from the touch screen input device. If the computer system is in a full power mode, the touch screen controller determines the input coordinates corresponding to the touch input, and transfers the input coordinates to a central processing system. If the computer system is in a power down mode, the touch screen controller asserts a main power on signal to a power subsystem, which causes the power subsystem to supply power to the central processing system according to the touch input.

Abstract: A system and process is provided which enables the dynamic mapping of texture to a variety of primitives, including complex primitives such as non-uniform rational B-spline surfaces (NURBS). The object, located in modeling coordinate (MC) space is parameterized to determine the parameter coordinate (PC) space associated with the object. This step is performed for an object and is readily applied to a variety of textures and views subsequently readied. Once the parameterization process has been performed, a mapping between the PC space and texture coordinate (TC) space is generated. This mapping, referred to herein as the .tau. mapping correlates the (s,t) coordinates of the PC space to the (u,v) coordinates of the TC space. The object is mapped from the MC space to the display coordinate (DC) and the .tau. mapping is then used to map the texture map onto the selected points of the object, such as the vertices of the object.

Abstract: An I/O streaming cache is provided to improve the data transfer bandwidth of an I/O bus of a computer system. The I/O streaming cache comprises at least one data array, a parent tag array, at least one child tag array, and control circuitry. The data arrays comprise a number of cache lines, each cache line having at least two cache line segments, for storing data being retrieved/prefetched during read operations and data being written during write operations. The parent tag array comprises a number of parent tag entries, one parent tag entry for each cache line, for describing a memory page being mapped by the corresponding cache line. The child tag arrays comprise a number of child tag entries, one child tag entry for each cache line segment, for describing the data blocks stored in the corresponding cache line segments. Each parent tag entry is parent to the child tag entries of the cache line segments of its corresponding cache line.

Abstract: A method and apparatus for implementing a zero latency synchronizer that permits the reliable transfer of data between clock domains by placing a metastability delay in the clock path. The zero latency synchronizer for synchronizing a signal from a first clock domain to a second clock domain is formed from a clock regenerator circuit and input and output master slave flip flops. The clock regenerator receives a first clock from the first clock domain and a second clock from the second clock domain and generates first and second regenerated clock signals. The first and second regenerated clock signals are formed in a manner that guarantees that the first and second regenerated clocks, in conjunction with the first and second clocks, can be used to control the input and output master slave flip flops and thereby pass data reliably from one clock domain to the other without delay.

Abstract: In a computer system having a number of page partitioned and virtually addressed address spaces, a physically addressed data storage structure and its complementary selection data storage structure is provided with a complementary memory page crossing prediction storage structure, a latch, and a comparator. The memory page crossing prediction storage structure is used to store a number of memory page crossing predictive annotations corresponding to the contents of the data and selection data storage structures. Each memory page crossing predictive annotation predicts whether the current access crosses into a new memory page. The latch is used to successively record a first portion of each accessing physical address translated from a corresponding portion of each accessing virtual address.

Abstract: A system for automatically encrypting and decrypting data packet sent from a source host to a destination host across a public internetwork. A tunnelling bridge is positioned at each network, and intercepts all packets transmitted to or from its associated network. The tunnelling bridge includes tables indicated pairs of hosts or pairs of networks between which packets should be encrypted. When a packet is transmitted from a first host, the tunnelling bridge of that host's network intercepts the packet, and determines from its header information whether packets from that host that are directed to the specified destination host should be encrypted; or, alternatively, whether packets from the source host's network that are directed to the destination host's network should be encrypted.

Abstract: A static logic circuit with improved output signal levels includes a static complementary MOSFET circuit with a signal node and pull-up and pull-down amplifiers, each with at least one biasing circuit, connected thereto. The pull-up and pull-down amplifiers are connected to VDD and VSS, respectively, and receive one or more logic signals (e.g. one for an inverter and more for logic gates such as AND, OR, etc.) and one or more bias signals and in accordance therewith provide pull-up and pull-down voltages, respectively, to the signal node. In accordance with the applied pull-up or pull-down voltage, the signal node charges to a charge state with an associated node voltage approximately equal to VDD or VSS, respectively. Each biasing circuit receives the same input logic signal as its associated pull-up or pull-down amplifier and provides thereto a bias signal approximately equal to VSS or VDD, respectively.

Abstract: A three-dimensional compact array of electronic circuitry includes a plurality of stacked modular compact arrays of electronic circuitry. Each modular compact array of electronic circuitry includes a substrate-less multi-chip module supporting a number of integrated circuits and interconnect which electrically connects the integrated circuits. Each modular compact array of electronic circuitry further includes an integrated heat exchanger and stacking connector supporting the substrate-less multi-chip module. The integrated heat exchanger and stacking connector includes a transverse connector region including a plurality of connector vias for connection to the interconnect of the substrate-less multi-chip module, and a transverse flow region including channels for circulating a coolant to remove heat from the substrate-less multi-chip module.