Abstract: A full width single in-line memory module (SIMM) for dynamic random access memory (DRAM) memory expansions. A printed circuit board having a multiplicity of DRAM memory elements mounted thereto is arranged in a data path having a width of 144 bits. The SIMM further includes on-board drivers to buffer and drive signals in close proximity to the memory elements. In addition, electrically conductive traces are routed on the circuit board to reduce loading and trace capacitance to minimize signal skew to the distributed memory elements. The SIMM further includes a high pin density dual read-out connector structure receiving electrical traces from both sides of the circuit board for enhanced functionality. The SIMM is installed in complementary sockets one SIMM at a time to provide memory expansion in full width increments.

Abstract: A frame buffer having a memory array, circuitry for accessing the array, a plurality of color value registers for storing a plurality of color values which may be written to the array, and circuitry for writing to the memory cells a data representing a single pixel, for writing simultaneously to the memory cells data representing a number of pixels equal to the number of conductors on the data bus, or for writing simultaneously to the memory cells data representing an entire row of pixels of the array.

Abstract: A wave propagation circuit having one or more circuit stages. Each circuit stage preferably has the same number of evaluation devices as the number of logic inputs into that circuit stage. The circuit stages alternately precharge and evaluate in a serial, wavelike manner responsive to a clock signal. During the precharge cycle of the clock, a precharge pulse propagates from circuit stage to circuit stage to precharge the output nodes of the circuit stages in a distributed, serial manner. During the evaluation cycle of the clock, a pulsed data signal permits the first stage to evaluate its inputs. Responsive to the output of the first circuit stage, a second circuit stage evaluates its inputs. The circuit further includes forward conduction devices and feedback devices to improve the noise margin and to reduce output errors caused by charge sharing and charge redistribution.

Abstract: A computer power system with a keyboard, a computer housing, and a single AC to DC power converter that generates a DC power signal as long as it is energized by an AC power source. The power system is digitally controllable by the central processing unit (CPU) or from soft on/off switches on the keyboard and computer housing. This is made possible by a soft on/off controller that receives soft on/off control signals from the CPU and the soft on/off switches and in response generates a power transition signal that triggers shaping circuits to connect (soft on) or disconnect (soft off) power system output lines and power lines from the converter. The shaping circuits also ensure that the rising edge of a digitally switched power system output signal resembles the rising edge of the converter's cold-start power signal.

Abstract: A computer-implemented method and system for of retrieving information. A first file of information is received which includes a first markup language to identify contents of the information. Responsive to the receiving the first file of information, the first file of information is parsed to generate a list of profiles, and at least one corresponding topic for each of the list of profiles. A second file in a second markup language is created containing the list of the profiles and at least one corresponding third file is created in a third markup language for the at least one corresponding topic for each of the list of profiles. The second file contains anchors referencing each at least one corresponding third file, and first markup instances in the first file of information are converted to second markup instances in either the second file or the third file.

Abstract: An inventive apparatus for generating a plurality of phase-shifted clocks on an IC, including a PLL disposed at a first location for generating a reference clock and a reference voltage, local clock generation circuit disposed at a second location, and a first conductor coupling to both the PLL and the local clock generation circuit for furnishing the reference clock from the PLL to the local clock generation circuit. The inventive apparatus further includes a second conductor coupling to both the PLL and the local clock generation circuit for furnishing the reference voltage from the PLL to the local clock generation circuit; wherein the plurality of phase-shifted clocks are generated at the second location, responsive to the reference voltage and the reference clock, using the local clock generation circuit.

Abstract: A logic signal validity verifier for use in determining the validity of the logic states of a group of logic signals includes an inactive signal fault monitor for determining when all of the logic signals are in an inactive signal state and an active signal fault monitor for determining when more than one of the logic signals are in an active signal state. Where the logic signals are differential, the logic signal validity verifier further includes a differential signal fault monitor for determining when corresponding pairs of the differential logic signals are in the same active or inactive signal state.

Abstract: An integrated circuit chip and flat capacitor assembly are connected with short bonding wires to reduce electrical noise. A flat chip capacitor is coupled to the chip and includes a first electrode, a second electrode and a dielectric layer disposed between the electrodes. The ground and power bonding pads of an integrated circuit chip are coupled to a number of terminals arranged in a row near the outer edge of the capacitor, where each of the terminals is coupled to one of the electrodes. The terminals of the capacitor are connected to a number of package leads of a lead frame or a other integrated circuit package. The invention includes embodiments in which the chip is placed on top of the capacitor, the capacitor is placed on top of the chip, and a flex circuit of a micro ball grid array is placed on a capacitor which is positioned on a chip.

Abstract: A frame buffer designed to be coupled to a data bus and to an output display in a computer system, the frame buffer including an array of memory cells for storing data indicating pixels to be displayed on the output display, address decoding apparatus for controlling access to the array, the address decoding apparatus including column address decoding apparatus for selecting groups of adjacent columns of the array, a plurality of apparatus for selectively writing to each of the columns of any of said groups of adjacent columns, a plurality of color value registers, latching apparatus for storing pixel data equivalent to a row of pixel data to be displayed on the output display, apparatus for writing pixel data from selected groups of adjacent columns of the array to the latching apparatus, and apparatus for connecting either selected ones of the color value registers, the latches, or the data bus to the apparatus for selectively writing to each of the columns of any of said groups of adjacent columns.

Abstract: A graphical user interface for displaying and selecting video programs, such as video on demand, includes a video on demand server coupled to a communication medium. A plurality of settop box receivers are coupled to the communication medium for receiving digitized programming in the form of movies and the like from the video on demand server. The settop box includes a central processing unit (CPU) coupled to a memory and other electronic modules. The CPU generates and displays the graphical user interface on the subscriber's television. The graphical user interface is based upon a metaphor in which a world of spaces are organized as part of a studio back lot through which a user may navigate. The back lot includes a Poster wall which presents to the user a series of movie posters representing available selections.

Abstract: A differential to single ended sense amplifier utilizes a minimum number of stages to convert a differential input signal received from complementary bit lines to a single ended output signal indicative of the state of the data stored in a selected memory cell connected to the complementary bit lines. The circuit is constructed to operate with low voltage swings, thereby increasing the switching speed and thus the sense speed. The sense amplifier includes power down capabilities and the ability to tristate its output terminal while in a standby mode of operation during which it is capable of reading the logic level of an input signal. In one embodiment, the output signal is latched using a simple register when the output stage goes tristated, to continue to provide a valid output signal while a subsequent sense operation is performed.

Abstract: A method is disclosed for loading a compiled test program into a microprocessor's internal caches and then controlling the execution of that program. Initially, the microprocessor's internal clock is disabled. Then for each memory location specified in the compiled program, the memory content associated with that location is loaded into the appropriate microprocessor cache. This is accomplished in two primary steps. First, the memory content is shifted into positions on the pins of the microprocessor by a boundary scan shift operation via an IEEE 1149.1 interface. Second, after the pins have the appropriate bit values for the current memory content, an external clock supplies the microprocessor with clock cycles that are then used by the microprocessor to control the loading of data/instructions from the pins into the appropriate data or instruction cache.

Abstract: Full-motion animation video is displayed in a computer system through use of sprite objects. The sprite objects define the images on the output display, and the locations of the sprite objects are changed to create the animation. The computer system includes three areas of physical memory assigned the status of a front buffer, a back buffer, and a cache buffer. The front buffer stores a frame currently displayed on the output display. The cache buffer is utilized to store a subset of the sprite objects so that all sprite objects need not be rendered for each frame of animation. The contents of the cache buffer are copied to the back buffer during display of the front buffer. To display a subsequent frame, the front and back buffers are switched. A cache buffer permits display of full-motion animation by minimizing use of processor and computer resources.

Abstract: A portable PCMCIA interface for a host computer having a system bus. In one embodiment, the host computer is a SPARC based computer having an SBus and running the UNIX operating system. The PCMCIA interface provides a user application with access to a PCMCIA card. In this embodiment, the PCMCIA interface includes software and hardware components. The software component includes a hardware-independent portion and a hardware-dependent portion. By implementing the software in a suitable high level language such as "C", the software can be easily ported to other hardware platforms by merely adapting the hardware-dependent portion. The hardware component includes an ASIC coupled between the system bus and a couple of PCMCIA sockets. In some embodiments, the hardware also includes a 5 volt to 12 volt DC--DC converter between the system bus and the PCMCIA sockets.

Abstract: A floating-point processor implements specialized graphics micro instructions. The specialized graphics micro instructions include a swap micro instruction which causes a hardware remapping of general purpose register groups to sort triangle vertices. The specialized graphics micro instructions also include specialized conditional branches for three dimensional geometry.

Abstract: A method and structure for controlling ground bounce and power supply noise during switching is provided in which a plurality of pull-up and/or pull-down transistors are provided whose turn on during switching is controlled in order to provide the desired slew rate in order to control the deleterious effects of ground bounce and power supply noise. In one embodiment, a plurality of pass transistors are used in order to delay a logical signal in order to control the slew rate. In one embodiment, these pass transistors are sensitive to ground bounce, providing a positive feedback mechanism to further enhance the control of ground bounce. In one embodiment, an RC network is conveniently formed in order to control slew rate, and in one embodiment the RC network is sensitive to ground bounce, providing positive feedback in order to further control the slew rate as a result of detected ground bounce.

Abstract: The multiple-input OR-gate includes a set of pull down transistors connected in parallel to a common signal line. A pair of first and second inverters are connected along the common signal line between the input pull down transistors and an output. A feedback element connects an output of the second inverter to an input of the first inverter. The inverters are configured to maintain the input of the first inverter at a first intermediate voltage level of V.sub.cc -2 Vt. Input signals received by the input transistors cause the voltage on the signal line to be pulled from the first intermediate level toward Vss. The first inverter responds by generating an output signal which swings from a low voltage of V.sub.ss towards a second intermediate level of V.sub.cc -0.7 Vt. The second inverter responds by generating an output signal which swings between the high level of V.sub.cc and a low level of V.sub.ss.

Abstract: The disclosed invention is a method and apparatus for use in handling interrupts in a data processing system where the kernel is preemptible, has real-time scheduling ability, and which supports multithreading and tightly-coupled multiprocessors. The invention more specifically provides a technique for servicing interrupts in a processor by means of kernel interrupt handler threads which service the interrupt from start to finish. For efficiency, the interrupt handler threads do not require a complete context switch unless the interrupt handler thread is blocked. The kernel makes use of preprepared interrupt handler threads for additional efficiency, and these interrupt handler threads are not subjected to inordinate delays caused by the phenomenon of interrupt priority inversion if they do become blocked.

Abstract: A method and apparatus for implementing self-organization in a wireless local area network ("LAN"). Each LAN is divided into a plurality of cells. Each cell is occupied by a number of nodes and one or more relay points (RPs) for communicating information within and among cells. Two separate channels are provided. The first channel, the control channel, is common to all RPs and accessible by all nodes and is utilized for communication of control information such as signal strengths of the RPs and the operating parameters of the selected RP. The second channel, the data channel, is utilized for normal communications between the selected RP and the node, and is specific to the RP. To initiate the self-organization process, the node identifies relay points in the LAN by acquiring identification information transmitted by the relay points across a common control channel.

Abstract: A fault tolerant, magnetic disk drive array with error detection and correction. The present invention performs vertical parity checks and one or two additional diagonal parity checks on a data stream as it is read into a disk drive array. The results of these "read-in" parity checks are stored in either two or three redundant disk drives. Upon read out of the data stream from the disk drive array, similar "read-out" parity checks are performed on the data. Based upon a comparison of the "read in " and read "out" vertical and diagonal parity checks, corrupted data can be detected and corrected.