Abstract: A method and apparatus is disclosed for advantageously implementing a full boundary scan test of input and bi-directional paths of an integrated circuit. The present invention provides a full boundary scan test capability with practically no degradation of speed of operation during normal operation of the integrated circuit. Within the integrated circuit under test, boundary scan registers are coupled to each input and bi-directional pin. When placed in a test mode, the corresponding output drivers are tristated for every bi-directional pin of the integrated circuit under test. Then the values of a test signal vector asserted on the pins of the integrated circuit are captured by the boundary scan registers. These captured values are retrieved and output from the integrated circuit so that they can be compared to the asserted test signal vector.

Abstract: A computer microphone with a dual power source capability is disclosed. This dual power source capability allows the microphone to receive power from an internal power source or an external power source disposed in computer hardware. In the event that the computer microphone is receiving power from the internal power source, and power is thereafter provided from the external source disposed in computer hardware, the present invention provides for the automatic turning off of the internal power source. In related fashion, in the event the computer microphone is receiving power from the external power source disposed in the computer hardware, and that external power source is thereafter turned off, the present invention automatically provides the computer microphone with power from the internal power source.

Abstract: An inorganic chip-to-package interconnection circuit is described. The circuit has a set of electrical conductors that are held together by a set of insulating inorganic tie bars. The circuit constitutes a high-density chip-to-package interconnection circuit that does not absorb vapor or volatile gases. A variety of methods for forming the circuit are described. Advantageously, the methods utilize known processing techniques.

Abstract: A method and apparatus for quickly copying a first frame region into a second frame region. A video memory array comprising a plurality of video random access memory devices is divided into at least two frame regions. A background image is rendered by a central processing unit into a background frame region within the video memory array. The central processing unit then requests the background image in the background frame region to be copied into a new frame region in the video memory array. A dedicated circuit copies the entire background image in the background frame region into the new frame region. The dedicated circuit operates by using a serial data register within each video random access memory device during the vertical retrace period of a video timing signal. The dedicated circuit performs the background frame copy without requiring any processing resources from the central processing unit.

Abstract: A digital system including a synchronizer circuit which significantly reduces the occurrence of metastability conditions during data transfer between a first digital subsystem and a second digital subsystem is disclosed. The synchronizer circuit includes a master synchronizer cell and a slave synchronizer cell for handling data transfer from the first subsystem to the second subsystem. Each synchronizer cell includes a signal node, a discharge node, a first discharge patch and a second discharge path, both coupled between the signal node and the discharge node, and a control element coupled to the first discharge path and the second discharge path. The control element selectively activates the first discharge path and the second discharge path in response to an input signal.

Abstract: An integrated circuit includes a bipolar logic stage and a CMOS logic stage. The bipolar logic stage includes a common emitter line positioned along a central axis, and a set of bipolar signal drive blocks arranged along the central axis. Each of the bipolar signal drive blocks includes a bipolar transistor with an emitter connected to the common emitter line. Each of the bipolar signal drive blocks further includes an emitter-base reverse voltage protection device. The CMOS logic stage includes a plurality of CMOS logic blocks connected to the set of bipolar signal drive blocks. The CMOS logic blocks are arranged in a compact configuration that is substantially perpendicular to the central axis. The CMOS logic stage performs logical operations on a set of input signals to generate a set of intermediate signals that are driven by the set of bipolar signal drive blocks onto the common emitter line.

Abstract: In a pipelined processor, an instruction queue and an instruction control unit is provided to group and issue m instructions simultaneously per clock cycle for execution. An integer and a floating point function unit capable of generating n.sub.1 and n.sub.2 integer and floating point results per clock cycle respectively, where n.sub.1 and n.sub.2 are sufficiently large to support m instructions being issued per clock cycle, is also provided to complement the instruction queue and instruction control unit. The pipeline stages are divided into integer and floating point pipeline stages where the early floating point stages overlap with the later integer pipeline stages. The instruction queue stores sequential instructions of a program and target instructions of a branch instruction of the program, fetched from the instruction cache.

Abstract: A computer system includes bus bandwidth management for operation of a high-speed bus. The high-speed bus is coupled to a plurality of modules. A plurality of client applications operate on the computer system, and request services from the high-speed bus to transfer data from a source module to at least one destination module. The bus bandwidth management system contains a bus manager, a dispatcher, a global controller, and a local controller contained on each module. Transfer requests for data transfer on the high-speed bus are made from the client applications to the bus manager. The bus manager takes the requested information and, based on a bus management policy management in effect, schedules a transfer order for the transfer requests. The bus manager then transfers the ordered transfer requests to the dispatcher. The dispatcher decomposes the ordered transfer requests into individual bus transfer operations.

Abstract: An apparatus and method are disclosed for minimizing the space required for a disk drive housing by mounting a disk drive unit in an enclosure of minimum size, using only a connection on one side of the disk drive and a drive belly plate, which is mounted on the bottom side of the disk drive, connected to an engaging surface on the bottom or intermediate cross-member of the superstructure, whereby the disk drive is held securely. The apparatus may accommodate four 3.5 inch form factor full height disk drives or six 3.5 inch form factor one inch high disk drive units. Additional space savings in the housing are achieved by the use of a unique electrical-connector attachment plate for connecting the cable connector terminals to the housing without the use of the normal connectors such as screws, bolts, etc.

Abstract: A frame buffer for accelerating the display of graphics data on an output display device which frame buffer includes a pair of color value registers each of which may be loaded with color values prior to writing to the frame buffer. Selection means are provided for selecting pixel data from the bus, from a first of the color value registers, from the second of the color value registers, or from both color value registers simultaneously. When data is written to the frame buffer from color value registers it may be written to a number of pixel positions simultaneously.

Abstract: The invention provides a method and apparatus for a memory device interface between a memory device and a CPU as well as the dimensions of the memory device. An electric circuit of the present invention has one-hundred-twenty pins along the length of the housing. The housing of the memory device has a length of approximately 85.6 mm and a width of approximately 54.0 mm. The left and right side socket interface portions of the housing have a minimum width of approximately 3.3 mm. The top socket interface portion has a maximum thickness of approximately 3.5 mm and a minimum height of approximately 3.0 mm. The bottom socket interface portion has a maximum thickness of approximately 5.0 mm and a minimum height of approximately 10.5 mm. Furthermore, the memory device interface portion of the present invention includes at least one pin which provides access to an address signal which indicates a memory array address location within the memory device.

Abstract: A method and apparatus for synchronizing pixel data flow within a memory display interface (MDI) to enable variable pixel depths, and to support display devices requiring differing pixel rates. A clock circuit receives a pixel clock from a DAC, and generates a shift clock (VSCLK), a pipeline clock, and an input control signal, all of which are synchronized to the pixel clock. The pixel clock synchronizes color pixel data transfer from the MDI to the DAC. The pipeline clock synchronizes pixel data processing through a pixel processing pipeline according to the frequency of the pixel clock and the number of pixels processed in parallel through the pixel processing pipeline. The input control signal feeds the pixel data from a VRAM frame buffer into the pixel processing pipeline according to the pixel depth mode, the frequency of the pixel clock, and the number of pixels processed in parallel through the pixel processing pipeline.

Abstract: A frame buffer including an array of memory cells, circuitry for accessing the memory cells to derive selected pixel data, and output circuitry for providing data signals at an output port, the output circuitry including circuitry for determining the precise time required for a data signal to rise and fall at the output port, such circuitry being selected to provide the minimum delay between succeeding data signals at the output port.

Abstract: A method and apparatus for removing a page table entry from a plurality of translation lookaside buffers ("TLBs") in a multiprocessor computer system. The multiprocessor computer system includes at least two processors coupled to a packet-switched bus. Page table entries are removed from a plurality of TLBs in the multiprocessor computer system by first broadcasting a demap request packet on the packet-switched bus in response to one of the processors requesting that a page table entry be removed from its associated TLB. The demap request packet includes a virtual address and context information specifying this page table entry. Controllers reply to the demap request packet by sending a first reply packet to the controller that sent the original demap request packet to indicate receipt of the demap request packet.

Abstract: A cache tag controller for a cache tag memory for receiving multiple consecutive cache tag modify operations through a system bus to update cache tags in the cache tag memory.

Abstract: A single-ended sense amplifier circuit for sensing the state of a bitline in a read-only memory. The sense amplifier includes an output circuit having an input and an output, the output for indicating a state of the bitline in response to a bitline voltage level. A precharge circuit is coupled to the input for charging the input to a first voltage level when the input is decoupled from the bitline. A discharge circuit is coupled between the bitline and the input. In one embodiment, the discharge circuit includes a field effect transistor coupled as a cascode device for coupling and decoupling the input to the bitline. The discharge circuit couples the input to the bitline when the discharge voltage level exceeds a threshold voltage level of the discharge circuit.

Abstract: A method and apparatus is provided for integrating a logic level simulation with an instruction level simulation for more accurate and faster system level simulation for testing. A host system or processors (CPU) is simulated by the instruction level simulator and the simulation of an input/output subsystem is modeled by the logic level simulator. The two simulations work side by side communicating through an interprocess communication (IPC) device and both simulations can perform a read/write access. Hence, a DMA and a slave access can occur at the same time causing a deadlock situation where both simulators are waiting for data and acknowledgment from each other at the same time. An input/output subsystem SBus module resolves this deadlock by deferring the non-DMA transaction. Finally, the synchronization of the two simulations is handled by the invention allowing the two simulators to run as asynchronous peers.

Abstract: A method and apparatus is disclosed for protecting a solder pad for a chip on tape packaged integrated circuit mounted on a surface of a printed circuit board that is exposed to a wave soldering operation. A pad cover may be used to protect the solder pad. The pad cover is mounted over the solder pad in a manner that protects the solder pad from being exposed to solder during the wave solder operation. After the wave solder is completed, the cover is removed and the leads of the chip on tape packaged integrated circuit are connected to associated solder pad traces on the printed circuit board. This type of arrangement is particularly useful in arrangements which require a heat sink to cool the chip on tape packaged integrated circuit.

Abstract: An efficient high-speed ECL to CMOS logic converter for BiCMOS integrated circuits. In one embodiment, a differential amplifier compares an ECL input signal to an ECL reference voltage and generates a pair of complementary intermediate signals on a corresponding pair of differential output nodes. The differential amplifier has two load resistors coupled in series with a common load resistor which limits the upper voltage swing at the differential output nodes. A regenerative stage coupled to the differential output nodes switches between a partially on state and a fully on state in response to the complementary intermediate signals. A pair of inverter stages convert the complementary intermediate signals into a pair of CMOS level signals. A pair of complementary output drivers coupled to the respective complementary inverter stages provide current driving capability.

Abstract: A dynamic logic circuit with reduced charge leakage includes a dynamic complementary MOSFET logic circuit with a P-type MOSFET, a number of N-type MOSFETs and a static CMOSFET inverter circuit. In response to a low clock signal, the P-type MOSFET turns on and charges the precharge node to a precharged node voltage. Some of the N-type MOSFETs are interconnected to form a logic circuit to logically process incoming logic signals and in accordance therewith selectively provide a conduction path for electrical charges from the precharge node. In response to a high clock signal, another N-type MOSFET turns on and together with the logic circuit conditionally discharges the precharge node via the logic circuit conduction path to a discharged node voltage. The value of the discharged node voltage is intermediate to the precharged node voltage and the circuit reference node voltage (e.g. VSS=0). The inverter circuit inverts and buffers the precharged and discharged node voltages.