Abstract: A network video server apparatus and method for transferring video image data across a computer network serving multiple clients. The network server apparatus comprises two parts, a server and a client. The server is run on a computer system containing a video digitizer hardware. Running the server on this computer system makes it possible to distribute video images across an existing network linking several client computer systems. The client provides the user with a means of viewing the images generated by the server through the network, controlling the size and type of image to be sent by the server, controlling the underlying video digitizer hardware, and collecting statistics about the server/client performance. The client software is designed to appear to the users as if they were operating the client software locally. The server and client communicate with each other over two channels: one for control information and another for video data.
Abstract: A frame buffer including a plurality of array planes of memory cells, row decoding circuitry for selecting rows of memory cells in each of the array planes to be accessed, column decoding circuitry for selecting columns of memory cells in each of the array planes to be accessed, a plurality of bitlines associated with the columns of memory cells of each array plane, each of the bitlines connecting to a column of memory cells and including a bitline sensing amplifier and a column select switch for providing access to the memory cells of that column of the array plane, a plurality of output sense amplifiers adapted to be connected to a selected number of bitlines in an array plane by closing of particular ones of the column select switches in the bitlines, first apparatus for providing output signals from the plurality of output sense amplifiers associated with each array plane to a data bus, and second apparatus for providing output signals from the plurality of output sense amplifiers associated with each arr
Type:
Grant
Filed:
October 29, 1993
Date of Patent:
August 15, 1995
Assignees:
Sun Microsystems, Inc., Samsung Semiconductor Inc.
Inventors:
Shuen C. Chang, Hai D. Ho, Szu C. Sun, Jawii Chen
Abstract: A multimedia display and editing system for editing multimedia projects on a display screen. A computer display screen is presented to the user which provides three different views of multimedia information. The first view is the Player which resembles a virtual video recorder with a display monitor. The second view is a story board which is very similar to a traditional story board. The third view is the Strip Viewer which presents the user with a time-line based view of the multimedia information. On the Strip Viewer display is an innovative screen tool referred to as a "Splinder", which is used for editing the beginning and ending points of displayed multimedia tracks. The Splinder splits two segments of multimedia information. The Splinder can be used to edit the ends of the two multimedia information segments.
Abstract: A caching arrangement which can work efficiently in a superscaler and multiprocessing environment includes separate caches for instructions and data and a single translation lookaside buffer (TLB) shared by them. During each clock cycle, retrievals from both the instruction cache and data cache may be performed, one on the rising edge of the clock cycle and one on the falling edge. The TLB is capable of translating two addresses per clock cycle. Because the TLB is faster than accessing the tag arrays which in turn are faster than addressing the cache data arrays, virtual addresses may be concurrently supplied to all three components and the retrieval made in one phase of a clock cycle. When an instruction retrieval is being performed, snooping for snoop broadcasts may be performed for the data cache and vice versa. Thus, for every clock cycle, an instruction and data cache retrieval may be performed as well as snooping.
Type:
Grant
Filed:
April 29, 1992
Date of Patent:
August 8, 1995
Assignee:
Sun Microsystems, Inc.
Inventors:
Norman M. Hayes, Adam Malamy, Rajiv N. Patel
Abstract: A draw processor for a graphics accelerator is disclosed that performs edgewalking and scan interpolation functions to render a three dimensional geometry object defined by a draw packet. The draw processor renders a subset of pixels on a scan line, such that a set draw processors taken together render the entire geometry object. The draw processor renders pixels into an interleave bank of a multiple bank interleaved frame buffer. The draw processor also processes direct port data through a direct port pipeline.
Abstract: A fast static logic gate contains a pullup logic network and a pulldown logic network configured to implement a logic function. The pullup logic network is coupled to receive gate inputs, and generates a first voltage level at a first node to represent a first state in accordance with the gate inputs and logic function. The first voltage level is less than the source voltage for the fast static logic gate circuit. A leaker circuit generates a second voltage level at the first node in response to a second state of the logic function. A driver circuit is coupled to a second node for generating an output. The pulldown logic network receives the gate inputs, and generates a second voltage level for the output to represent the second state in accordance to the gate inputs and logic function. The switch circuit couples the first node to the second node when the logic function generates the second state, and couples the source voltage to the second node when the logic function generates the first state.
Abstract: A write-back cache control system having a pending write-back cache controller in a multiprocessor cache memory structure. The processor subsystems in the multiprocessor system are coupled together using a high-speed synchronous packet switching bus called a memory bus. Each processor subsystem has an associated cache control system. When a processor's cache control system does not have a required memory location in the cache memory, it broadcasts a memory request packet across the memory bus for the required data. If an owned cache line is being replaced, the cache control system copies the old cache line data to the pending write-back cache controller which is responsible for the write-backs of owned cache lines to main memory. The cache control system then transfers ownership of the old replaced cache line to the pending write-back controller.
Type:
Grant
Filed:
November 9, 1992
Date of Patent:
July 18, 1995
Assignees:
Sun Microsystems, Inc., Xerox Corporation
Inventors:
Bjorn Liencres, Douglas Lee, Pradeep S. Sindhu, Tung Pham
Abstract: An improved attachment mechanism for attaching the motherboard in a computer system to its chassis is disclosed. The attachment mechanism includes a rail that engages at least two opposing edges of the motherboard and a hook mechanism that engages a catch formed in the chassis. The hook mechanism is secured to a central portion of the motherboard. The rail and hook mechanism cooperate to securely couple the motherboard to the chassis without requiting the use of extensive usable space on the motherboard. The described arrangement permits the motherboard to be quickly and easily installed and released.
Type:
Grant
Filed:
January 13, 1994
Date of Patent:
July 18, 1995
Assignee:
Sun Microsystems, Inc.
Inventors:
James Testa, Joseph M. Spano, William L. Dailey, Daniel D. Gonsalves, Robert S. Antonuccio, James M. Carney, Mathew J. Palazola
Abstract: In a bit mapped display environment which has n hardware color look-up tables (CLUTs) where n=1 or more, which also has a limited number of Display Attribute Identification Values, and which may operate under various window systems, such as the X Window System protocol, an apparatus and a method for installing and uninstalling hardware colormaps under the constraint of a finite number of Display Attribute Identification Values, whereby the most recently installed (MRI) policy of the X Window System is followed. The invention provides a scheme which gracefully degenerates to some "color flashing" when Display Attribute Identification Values are exhausted; which allows Display Attribute Identification Values to be uncoupled from colormap management and used for more graphics intensive functions when needed; and which dynamically regenerates when display attributes again become available.
Type:
Grant
Filed:
March 29, 1994
Date of Patent:
July 4, 1995
Assignee:
Sun Microsystems, Inc.
Inventors:
Paolo Sabella, Jerald R. Evans, Deron Johnson
Abstract: A high speed inverter circuit is disclosed. The inverter has a quiescent state, a set state for receiving an input pulse and generating a set pulse in response thereto, a reset stage in which a delayed version of the same input pulse is used to reset the inverter, and a recovery state for preparing the inverter for the arrival of a new input pulse. The inverter has an extremely fast switching speed because virtually all of the available energy of the input signal is used to set the inverter. The inverter may be used in an inverter chain for rapidly propagating electrical signals.
Abstract: A set in structure (SIS) list is established for each DAG structure of a DAG structure network. Additionally, a used before set (UBS) list is established for each structure invoking element in the DAG data structure. At each invocation of a DAG structure, a list of traversal state list (TSL) attribute values that need to saved and subsequently restored (SAR) for the invoking DAG data structure is established. The SAR list of an invoked DAG data structure is established based on a list of attributes needed by the invoking DAG data structure (N) and the SIS of the invoked DAG data structure. The N list is established based on the UBS list of the invoking structure element of the invoking DAG structure, and a need from child (NFC) attribute list of the invoking DAG data structure. Only values of the TSL attributes included in the SAR list are saved before the invoked DAG data structure is traversed.
Abstract: The present invention enables a computer system to store from register files to memory, and restore from memory back to the register files, data from programs designed to operate in accordance with a first word size, as well as programs designed to operate in accordance with a second word size. This is accomplished without an increase in hardware and without requiring modification of existing software. In particular, an indication is utilized at the procedure level to designate whether a particular procedure is using words of a first or second word size. Preferably, this indication is placed in a first predetermined bit position in the stack pointer of the procedure. When a save occurs, certain contents from the register file are saved to memory along with the stack pointer. Under certain circumstances, the word size indication is moved to a second predetermined bit position within the stack pointer which is stored in a predesignated stack pointer address in the save area.
Type:
Grant
Filed:
October 11, 1994
Date of Patent:
July 4, 1995
Assignee:
Sun Microsystems, Inc.
Inventors:
Michael Powell, Robert Cmelik, Shing Kong, David Ditzel, Edmund Kelly
Abstract: A high speed processing flip-flop contains a header circuit and a pulse flip-flop circuit. The header circuit is a clock pre-processing circuit that generates clock pulses for operation of the pulse flip-flop circuit, and the pulse flip-flop circuit is a single stage latch. The header circuit contains functional logic including the flip-flop functionality for the high speed processing flip-flop, and any additional processing functions, such as multiplexing. The header circuit also contains a pulse modulator that generates selected clock pulses, based on the functional logic, for the pulse flip-flop circuit. The pulse flip-flop circuit contains storage, a driver circuit, and, for each data input, an input buffer, and a pass gate. The pulse flip-flop circuit couples the data to the driver circuit and storage during an active clock pulse for the corresponding data. Consequently, data input to the pulse flip-flop is not delayed by logic processing.
Abstract: A translation lookaside buffer for use with a virtual memory system including apparatus for storing virtual addresses, apparatus for storing a physical address associated with each of the virtual addresses, some of the physical addresses corresponding to pages in which the information sought by the virtual address resides, and others of the physical addresses corresponding to pages in which the physical address of information sought by the virtual address resides.
Abstract: During code generation, a routine is first decomposed into regions. Then, starting from the highest plateau, i.e. the inner most control flow level, the interference graph of each region in a plateau is colored individually. Neighboring regions of the plateau are then combined by connecting the colored nodes of the interference graphs that are live at region boundaries. If connecting the interference graphs render the connected interference graph uncolorable, colored nodes that are live at region boundaries are connected by introducing register to register move or spilling the node. When all neighboring regions of a plateau are combined, the plateau collapses into a region of the lower level plateau. The process is repeated until all plateaus are collapsed and the regions of the base plateau are colored and combined together. Registers are then allocated to the colored nodes.
Abstract: The present invention is an option board protocol (OBP) PROM for interfacing an optional peripheral device or board with a host computer system without retrofitting the CPU PROM. In general, the CPU PROM does not recognize option boards unless they are known to the designer of the CPU PROM and properly controlled by built-in drivers of the CPU PROM as accessed through a ROMVEC Table of the CPU PROM. The OBP PROM allows the option board to participate in the Power On sequence just as other standard peripheral devices. During a POST sequence, the CPU activates the OBP code, installs the diagnostics, and then the OBP PROM tests the option board itself, using tools provided by the CPU PROM. The OBP PROM may load its own driver before completing the POST sequence. The OBP support code in the CPU PROM provides three new functions to reduce the duplication of code, to standardize the testing methods and to streamline the diagnostic functions of the POST sequence.
Abstract: The present invention includes a first data processing device (node I) coupled to a first private network and to a firewall server (FWA). Firewall server FWA is in turn coupled to a public network, such as the Internet. A second data processing device (node J) is coupled to a second private network which is coupled to the Internet through a firewall server (FWB). Node I provides a data packet including IP data and a destination address for the intended receiving node J to firewall FWA. Firewall FWA is provided with a secret value a, and a public value .varies..sup.a mod p. Similarly, firewall FWB is provided with a secret value b and a public value .varies..sup.b mod p. The firewall FWA obtains a Diffie-Hellman (DH) certificate for firewall FWB and determines the public value .varies..sup.b mod p from the DH certificate. Firewall FWA then computes the value of .varies..sup.ab mod p, and derives a key K.sub.ab from the value .varies..sup.ab mod p. A transient key K.sub.