Abstract: A method is provided. A multi-amplitude signal is received and downconverted so as to generate I and Q signals using a local oscillator signal. The I and Q signals are equalized, and the equalized I and Q signals are digitized. First and second gains are adjusted with the second and first digital signals, respectively, and applied to the equalized I and Q signals, respectively. The difference between the first and second amplified signals is determined, and an error signal is generated from the difference between the first and second amplified signals. The local oscillator signal is then adjusted with the error signal.

Abstract: A processing device includes a plurality of non-volatile logic element array domains having two or more non-volatile logic element arrays to store 2006 a machine state of the processing device stored in a plurality of volatile store elements. Configuration bits are read to direct which non-volatile logic element array domains are enabled first and to direct an order in which the first enabled non-volatile logic element array domains are restored or backed up in response to entering a wakeup or backup mode. Configuration bits can be read to direct an order of and a parallelism of how individual non-volatile logic element arrays in a first enabled non-volatile logic element array domain are restored or backed up. The order of restoration or backing up can be controlled by instructions from non-volatile arrays of the first enabled of the plurality of non-volatile logic element array domains.

Abstract: An apparatus is provided. Latches are coupled in series with one another in a ring configuration. Each latch includes a tri-state inverter, a first resistor-capacitor (RC) network, and a second RC network. The tri-state inverter has a first clock terminal and a second clock terminal. The first RC network is coupled to the first clock terminal. The second RC network is coupled to the second clock terminal. A biasing network is also provided. The biasing network has a first bias voltage generator that is coupled to the first RC network for each latch and a second bias voltage generator that is coupled to the second RC network for each latch.

Abstract: An intermediate set of bits of a SAR ADC are converted into first intermediate analog value and a second intermediate analog value respectively from a first set of representative capacitor and a second set of representative capacitor. A capacitor in the first set and second set are selected as not same. A SAR ADC output code is generated from the first intermediate analog value and the second intermediate analog value. The resolution of a N bit SAR ADC can be enhanced by generating more than one N bits digital codes correspondingly operating the N Bit SARADC with more than on transfer functions. Each transfer function is selected such that they are offset by a fraction of LSB value. The more than one N bits digital codes are then added to form P bits digital code such that P is greater than N due to addition.

Abstract: A method for die bonding includes positioning a dispenser in a die bonding apparatus, wherein the dispenser includes a reservoir having bonding adhesive therein including particles and a liquid carrier. The dispenser is moved to provide mechanical agitation to the dispenser for mixing the bonding adhesive into a homogeneous mixture of particles and the liquid carrier, wherein the bonding adhesive is not dispensed during moving. After the moving, the bonding adhesive is dispensed onto a bonding location on the workpiece without removing the dispenser from the die attach apparatus. An integrated circuit (IC) die is attached onto the bonding adhesive over the bonding location. The method can also include determining an amount of time elapsed after the last mixing of the bonding adhesive or the positioning of the dispenser in the die bonding apparatus, and automatically initiating movement for mixing only if the elapsed time exceeds a predetermined time.

Abstract: A system and method for managing power in a subnet having a hub in communication with one or more nodes is disclosed. The hub and nodes communicate using one or more non-contention access methods, such as scheduled, polled or posted access. The node may enter a sleep or hibernation state while no scheduled, polled or posted allocation interval is pending. The hibernation state allows the node to hibernate through one or more entire beacon periods. In the sleep state, the node may be asleep between any scheduled, polled and posted allocation intervals for the node or during another node's scheduled allocation interval in a current beacon period. By selecting which access scheme is in use, the node and hub can increase the node's chances to be in hibernation or sleep state and minimize power consumption.

Abstract: Connection circuitry couples scan test port (STP) circuitry to test access port (TAP) circuitry. The connection circuitry has inputs connected to scan circuitry control output leads from the TAP circuitry, a select input lead, and a clock input lead. The connection circuitry has outputs connected to a scan enable (SE) input lead, a capture select (CS) input lead, and the scan clock (CK) input lead of the STP circuitry. The connection circuitry includes a multiplexer having a control input connected with a clock select lead from the TAP circuitry, an input connected with a functional clock lead, an input connected with the clock input lead, an input connected with a Clock-DR lead from the TAP circuitry, an OFF lead, and an output connected with the scan clock input lead.

Abstract: An integrated circuit includes switching circuits for selectively connecting the bond pads to functional core logic and isolating the bond pads from second conductors, and the switch circuits for selectively connecting the bond pads to the second conductors to provide bi-directional connections between the bond pads on opposite sides of the substrate and isolating the bond pads from the functional core logic.

Abstract: A leadframe for a QFN/SON semiconductor device comprising a strip of a first metal as the leadframe core with a plurality of leads and a pad. a layer of a second metal over both surfaces of the strip. There are sidewalls normal to the surfaces. The first metal exposed at the sidewalls and at portions of a surface of the pad.

Abstract: An apparatus includes a plurality of die areas having integrated circuit (IC) die each having circuit elements for performing a circuit function, and scribe line areas between the die areas. At least one test module is formed in the scribe line areas. The test module includes a reference layout that includes at least one active reference MOS transistor that has a reference spacing value for each of a plurality of context dependent effect parameters, and a plurality of variant layouts. Each variant layout provides at least one active variant MOS transistor that provides a variation with respect to the reference spacing values for at least one of the plurality of context dependent effect parameters.

Abstract: Apparatus and method for improving throughput in a wireless device accessing coexisting networks. In one embodiment, a wireless device includes first and second wireless transceivers, a power state controller, and an access controller. The first wireless transceiver is configured to access a first wireless network. The second wireless transceiver is configured to access a second wireless network. The power state controller is configured to switch the first wireless transceiver between an active state and a sleep state. The power consumed by the first wireless transceiver while in the sleep state is reduced relative to the active state. The access controller is configured to alternately allocate a wireless medium to the first wireless transceiver and the second wireless transceiver. The power state controller and the medium access controller are configured to coordinate power state switching of the first wireless transceiver and wireless medium access by the second wireless transceiver.

Abstract: An electronic circuit (200) for use with an accessing circuit (110) that supplies a given address and a partial write data portion and also has dummy cycles. The electronic circuit (200) includes a memory circuit (230) accessible at addresses, an address buffer (410), a data buffer (440) coupled to the memory circuit (230), and a control circuit (246) operable in the dummy cycles to read data from the memory circuit (230) to the data buffer (440) from a next address location in the memory circuit (230) and to store that next address in the address buffer (410).

Abstract: Embodiments of the invention provide a DPD system where the transmit reference signal is transformed, including sub-sampling, frequency translation, and the like, to match the feedback signal, which goes thru a similar transformation process, to obtain an error signal. The same transformation is applied to a system model, which may be Jacobian, Hessian, Gradient, or the like, in an adaptation algorithm to minimize error.

Abstract: A wireless apparatus includes a wireless transceiver, a WLAN controller and a second controller coupled to the wireless transceiver. The WLAN controller is configured to send/receive packets in accordance with a WLAN protocol, and the second controller is configured to send/receive packets in accordance with a second wireless protocol. The apparatus includes scheduling logic that determines whether a WLAN communication will complete before an end of a WLAN active time period. If the scheduling logic determines that the WLAN communication will not complete before the end of the WLAN active time period, the scheduling logic causes the WLAN controller to transmit a WLAN packet that encodes a NAV value that prevents an access point from using the wireless medium until an end of second time period. The second controller is configured to use the wireless medium during the second time period.

Abstract: A power converter system is provided, comprising a plant having a plant input and a plant output; and a plant identification filter that receives the plant input and the plant output, and estimates the values of poles and zeros of the plant, wherein the plant identification filter updates the estimates of the poles and zeros, based upon the plant input and the plant output, beginning from an initial state; and a rate at which the plant identification filter updates the estimates of the values of the poles and zeros is slower than a rate at which the plant input and the plant output are received by the plant identification filter.

Abstract: A wireless communications device has two or more multiple port memory units operable to perform encryption/decryption shuffling and processing. Other circuits and methods of manufacture and operation are also disclosed.

Abstract: An integrated circuit with a passivation trapping layer. An integrated circuit with a hydrogen or deuterium releasing layer underlying a passivation trapping layer. Method for forming an integrated circuit having a hydrogen or deuterium releasing layer. Method for forming an integrated circuit having a passivation trapping layer.

Abstract: An operating system independent JTAG debugging system implemented to run in a web browser. The software executing in the browser identifies the JTAG enabled components in the target system that is to be tested, and automatically downloads the latest versions of the appropriate software, JTAG drivers and configuration information from a test server.

Abstract: An embodiment of the invention provides a method for decreasing power in a static random access memory (SRAM). A first voltage is applied between latch sourcing and latch sinking supply lines for columns of memory cells that are column addressed during a read cycle. A second voltage is applied between latch sourcing and latch sinking supply lines for columns of memory cells that are not column addressed during a read cycle. Because the second voltage is less than the first voltage, power in the SRAM is reduced. In this embodiment, a memory cell in the SRAM includes at least one read buffer and a latch connected between the latch sourcing and latch sinking supply lines.

Abstract: Systems and methods for designing, using, and/or implementing slotted channel access techniques in network communications are described. In some embodiments, a method may include selecting one of a plurality of time slots within a contention access period (CAP), each of the plurality of time slots having a predetermined duration, and transmitting a packet during the selected time slot. For example, the time slot may be selected randomly or based on a round-robin algorithm. In some implementations, the duration of each of the plurality of time slots may correspond and/or be equal to: (a) a duration of a data packet of maximum size, (b) a sum of durations of a request-to-send packet, an interframe space, and a clear-to-send packet, and/or (c) a duration of a guaranteed time slot (GTS) or contention free period (CFP) request packet, as prescribed by a given communication protocol or standard.