Abstract: An apparatus and method for charging a battery with improved charging performance and reduced degradation of the battery. A battery charging profile is configured to achieve minimal degradation of a selected battery possible for a given charge time. The minimization is achieved using battery degradation modeling data indicative of a battery degradation level of a selected battery, and voltage and temperature response modeling data indicative of predicted battery voltage and temperature of the selected battery as a function of time and charging current.

Abstract: An apparatus is provided. A comparison circuit is configured to receive an analog signal. A reference circuit is coupled to the comparison circuit and is configured to provide a plurality of reference signals to the comparison circuit. A conversion circuit is coupled to the comparison circuit and is configured to detect a change in the output of the comparison circuit. A time-to-digital converter (TDC) is coupled to the comparison circuit. A timer is coupled to the comparison circuit. A rate control circuit is coupled to the conversion circuit. An output circuit is coupled to the rate control circuit and the TDC, where the output circuit is configured to output at least one of a synchronous digital representation of the analog signal and an asynchronous digital representation of the analog signal.

Abstract: Key fob and vehicle control unit identifiers (IDs) are used for entity authentication or trust transfer to achieve a secured initial pairing. The key fob is capable of transmitting only (not receiving) and is paired with a control unit in a vehicle or with any other control device. Use of the key fob and control unit IDs prevents unauthorized pairing and access to the operation key (OpKey) that is later used for communications between the devices. Elliptical curve cryptography (ECC) is used for strong security and efficient implementation. In the pairing process, device IDs are used for entity authentication and public key cryptography is used for easy key management. Symmetric encryption is used for fast normal operation and to accommodate key fob addition or revocation after key fob loss.

Abstract: A method for determining a photovoltaic (PV) current from each of a plurality of PV elements arranged in a differential network is provided. The differential network is controlled with a plurality of control signals, where the differential network includes a plurality of inductors, and each control signal has a duty cycle. A plurality of controller parameters is received from the plurality of differential controllers. The PV current for each of the plurality of PV elements is calculated from the plurality of inductor currents and the duty cycle for each control signal.

Abstract: Piezoelectric harvesting devices are disclosed herein. An embodiment of a harvesting device includes a cantilever having a resonant frequency associated therewith, wherein the cantilever vibrates when in the presence of a vibration source, and wherein the harvesting device generates a current upon vibration of the cantilever. The generated current is present at an output. A bias flip circuit is used to tune the resonant frequency of the harvesting device based on measurements of the vibration source that causes the cantilever to vibrate, wherein the bias flip circuit includes a switch that connects and disconnects an inductor to the output.

Abstract: An integrated circuit containing an extended drain MOS transistor with deep semiconductor (SC) RESURF trenches in the drift region, in which each deep SC RESURF trench has a semiconductor RESURF layer at a sidewall of the trench contacting the drift region. The semiconductor RESURF layer has an opposite conductivity type from the drift region. The deep SC RESURF trenches have depth:width ratios of at least 5:1, and do not extend through a bottom surface of the drift region. A process of forming an integrated circuit with deep SC RESURF trenches in the drift region by etching undersized trenches and counterdoping the sidewall region to form the semiconductor RESURF layer. A process of forming an integrated circuit with deep SC RESURF trenches in the drift region by etching trenches and growing an epitaxial layer on the sidewall region to form the semiconductor RESURF layer.

Abstract: A method for intra-prediction estimation is provided that includes determining a best intra-prediction mode for a block of samples, wherein at least some of the neighboring samples used for intra-prediction estimation include approximate reconstructed samples, applying approximate reconstruction to the block of samples using the best intra-prediction mode to generate a block of approximate reconstructed samples, and storing the block of approximate reconstructed samples for use in intra-prediction estimation of other blocks of samples.

Abstract: Apparatus and method for processing a physical layer protocol convergence (PLCP) header. In one embodiment, a wireless device includes a PLCP header processor. The PLCP header processor is configured to: process a physical layer header, process a check value based on the physical layer header, and process an error correction code based on the physical layer header and the check value. A concatenation of the physical layer header, check value, and error correction code the PLCP header processor is configured to process consists of a number of information bits that is an integer multiple of a number of information bits per symbol used to encode the PLCP header.

Abstract: Disk drive pre-amplifier output stage circuitry is presented including a high pass input filter for removing DC offsets from differential read data signals and providing an input to AB drivers of the output stage, in which an offset test circuit selectively drives the high pass filter output nodes according to the offset at the filter input to facilitate measurement of the preceding circuit offset at the driver output terminals, and a common mode regulator circuit regulates common mode voltages at the first and second driver output nodes to a predetermined value in read and write modes.

Abstract: An integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series is disclosed. Each bipolar transistor includes a breakdown inducing feature. The breakdown inducing features have reflection symmetry with respect to each other. A process for forming an integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series, with breakdown inducing features having reflection symmetry, is also disclosed.

Abstract: A method is provided. An analog signal is received. The analog input signal is compared to first and second reference signals to generate a first comparison result, and the first comparison result and a first time stamp corresponding to the first comparison result are registered. A first portion of a digital signal is generated from the first comparison result. If the comparison result remains substantially the same for a predetermined interval, an ADC is enabled to generate a second comparison result at a sampling instant. A second time stamp that corresponds to the sampling instant is generated. The second comparison result and a second time stamp corresponding to the first comparison result are registered, and a second portion of the digital signal is generated from the second comparison result.

Abstract: A method is provided. An analog signal is received. The analog input signal is compared to first and second reference signals to generate a first comparison result, and the first comparison result and a first time stamp corresponding to the first comparison result are registered. A first portion of a digital signal is generated from the first comparison result. At least one of the first and second reference signals is adjusted. A second comparison result is generated if the analog signal reaches an adjusted one of the first and second reference signals within a predetermined interval, and a second portion of the digital signal is generated from the second comparison result.

Abstract: Systems and methods for fall-back rate-matching and timing for user equipment (UE) configured for downlink (DL) Coordinated Multi-Point Transmission (CoMP) are disclosed. In one embodiment, when a UE configured in DL CoMP receives a fall-back transmission, PDSCH is rate-matched around the serving cell CRS. In an alternative embodiment, when a UE configured in DL CoMP receives a fall-back transmission, PDSCH is rate-matched or uses timing around one of the cell-specific reference symbol (CRS) resource element (RE) set indicated by RRC-higher layer signaling. For example, PDSCH may be rate-matched or use timing around the first RRC higher layer configured CRS RE set.

Abstract: An integrated circuit containing a diode with a drift region containing a first dopant type plus scattering centers. An integrated circuit containing a DEMOS transistor with a drift region containing a first dopant type plus scattering centers. A method for designing an integrated circuit containing a DEMOS transistor with a counter doped drift region.

Abstract: A method of forming an IC including MOS transistors includes using a gate mask to form a first active gate feature having a line width W1 over an active area and a neighboring dummy feature having a line width 0.8 W1 to 1.3 W1. The neighboring dummy feature has a first side adjacent to the first active gate feature, and a nearest gate level feature on a second side opposite the first side. The neighboring dummy feature defines a gate pitch based on a distance to the first active gate feature or the neighboring dummy feature maintains a gate pitch in a gate array including the first active gate feature. The spacing between the neighboring dummy feature and the nearest gate level feature (i) maintains the gate pitch or (ii) provides a SRAF enabling distance that is ?2 times the gate pitch and the gate mask includes a SRAF over the SRAF distance.

Abstract: Method and apparatus for multiplying a signed first operand na bits and a signed second operand nb bits, wherein na and nb are different positive integer numbers, the method comprising generating single bit products of pairs of a single bit from the signed first operand and a single bit from the signed second operand with a logical AND function to produce na times nb single bit products, selectively inverting for the signed first operand and the signed second operands the single bit products of the first operand bit na-1 multiplied with the second operand bits 0 to nb-2, selectively inverting the single bit products of the signed second operand bits 0 to na-2 multiplied with the signed second operand bit nb-1, after the step of inverting adding the single bit products in accordance with their respective order for producing an intermediate product, and adding a ‘1’ bit value at bit positions nb-1, na-1 and na+nb-1 for receiving a final product.

Abstract: An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A dedicated scan cell has a functional data output separate from a test data output. Shared scan cells each have a combined output for functional data and test data. The shared scan cells are coupled in series. The test data input of the first shared scan cell is connected to the test data output of the dedicated scan cell. The combined output of one shared scan cell is coupled to the test data input lead of another shared scan cell. The multiplexer has an input coupled to the test data output, an input connected to the combined output lead of the last shared scan cell in the series, and an output connected in the scan path.

Abstract: A semiconductor wafer handler comprises a ring (70) attached to a hub (80) by a plurality of spokes (90). Vacuum is applied to the surface of the semiconductor wafer through orifices (100) containing in the ring (70). Water and/or nitrogen can be applied to the surface of the semiconductor wafer through orifices (110) contained in the spokes (90).

Abstract: A method of forming a capacitor structure comprises: forming a doped polysilicon layer on an underlying dielectric layer; forming a dielectric stack on the doped polysilicon layer; forming a contact hole in the dielectric stack to expose a surface region of the doped polysilicon layer; forming a conductive contact plug that fills the contact hole and is in contact with the exposed surface of the doped polysilicon layer; forming a plurality of trenches in the dielectric stack such that each trench exposes a corresponding surface region of the doped polysilicon layer; forming a conductive bottom capacitor plate on exposed surfaces of the of the dielectric stack and on exposed surfaces of the doped polysilicon layer; forming a capacitor dielectric layer on the bottom capacitor plate; and forming a conductive top capacitor plate on the capacitor dielectric layer.

Abstract: A display uses x illuminator systems to produce x primary colors and y overlap colors, which are combinations of primary colors, to illuminate a spatial light modulator in a display system. A first set of n duty cycles for the x primary colors over a frame is provided, wherein the display system can select any one of the duty cycles to produce a desired white point. A second set of n duty cycles of x+y colors over a frame corresponding to the first set of duty cycles is determined, where the second set of duty cycles are generated responsive to a specified desired allocation of the frame to the y overlap colors, such that each of the overlap colors can be displayed from a dark shade to a bright shade while maintaining a constant color point.