Abstract: A low power sound recognition sensor is configured to receive an analog signal that may contain a signature sound. Sparse sound parameter information is extracted from the analog signal and compared to a sound parameter reference stored locally with the sound recognition sensor to detect when the signature sound is received in the analog signal. A portion of the sparse sound parameter information is differential zero crossing (ZC) counts. Differential ZC rate may be determined by measuring a number of times the analog signal crosses a threshold value during each of a sequence of time frames to form a sequence of ZC counts and taking a difference between selected pairs of ZC counts to form a sequence of differential ZC counts.

Abstract: The differential signals at the outputs of a differential amplifier quickly change in response to common mode changes in the output differential signals. The amplified input signals amplified by the differential amplifier quickly change in response to common mode changes in the differential signals input into the differential amplifier. A bias voltage input to the differential amplifier is isolated to remove low-frequency components from the bias voltage.

Abstract: The barrier-aware bridge tracks all outstanding transactions from the attached master. When a barrier transaction is sent from the master, it is tracked by the bridge, along with a snapshot of the current list of outstanding transactions, in a separate barrier tracking FIFO. Each barrier is separately tracked with whatever transactions that are outstanding at that time. As outstanding transaction responses are sent back to the master, their tracking information is simultaneously cleared from every barrier FIFO entry.

Abstract: One example includes an amplifier system. The system includes a precision amplifier portion comprising a first input stage configured to receive an input voltage and a first output stage configured to generate an output voltage at the first output stage based on the input voltage. The system also includes a slew amplifier portion arranged in parallel with the precision amplifier portion and comprising a second input stage that receives the input voltage and a second output stage. The slew amplifier portion can be activated in response to a detected slew condition associated with the input voltage to generate the output voltage based on the input voltage.

Abstract: A buck switching voltage regulator, with high side and low side switching transistors, includes mode control circuitry for switching between PWM and PFM modes based on sensing inductor current through the low side switch during switching cycle OFF times (inductor discharge). Mode switching is based on comparing a an integrated inductor current sense signal with an integrated reference signal corresponding to a predefined average inductor current IAVE. In one embodiment, a mode switching condition is based in part on [IVALLEY=2IAVE?IPEAK], where IPEAK is a detected peak inductor current at the beginning of an OFF time, and IVALLEY is an inductor current value determined by IAVE and IPEAK.

Abstract: A method includes simulating transmission of multiple symbols representing multiple bits over at least one communication channel, where the multiple symbols are associated with a polar code. The method also includes identifying error rates of equivalent bit channels associated with the simulated transmission of the symbols. The method further includes selecting a specified number of the bits as frozen bits in the polar code using the identified error rates. Simulating the transmission of the symbols could include computing log likelihood ratio (LLR) values associated with the equivalent bit channels and simulating polar decoding of received symbols using the LLR values. Identifying the error rates could include calculating means and variances of the LLR values associated with the equivalent bit channels and identifying probability density functions of the LLR values using the means and variances. The selected bits could represent the specified number of bits identified as having worst error rates.

Abstract: A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power supply voltage levels can be applied to the source nodes of the load transistors (or both). Asymmetric bias voltages applied to the transistors in this manner will reduce the transistor drive current, and can thus mimic the effects of bias temperature instability (BTI). Cells that are vulnerable to threshold voltage shift over time can thus be identified.

Abstract: A method for signaling sample adaptive offset (SAO) band offset syntax elements in a video encoder is provided that includes receiving a plurality of band offset syntax elements, entropy encoding an absolute value of a magnitude of each band offset syntax element in a compressed video bit stream, and entropy encoding a sign of each non-zero band offset syntax element in the compressed video bit stream following the absolute values of the magnitudes.

Abstract: This invention is a signal input/output design tool for integrated circuit input/output design. The connectivity capacity of at least multiplexer connecting internal signals and external lines is expressed as a first set of Boolean expressions. The desired connectivity between internal signals and external lines is expressed is provided by a designer. A programmed general purpose computer expresses the desired connectivity as a second set of Boolean expressions and determines whether said first set of Boolean expressions and said second set of Boolean expressions are Boolean satisfiable. If satisfiable, the design tool generates control signals to configure the at least one multiplexer to achieve the desired connectivity. If not satisfiable, the design tool generates a report indicating which portions of the desired connectivity are achievable and which are not.

Abstract: A method of registering terminals on an interdigitated chip capacitor (“IDC”) with a plurality of contact pads on a substrate. At least one vertically extending nonconductive abutment surface is formed between adjacent ones of the contact pads. A plurality of grooves projecting outwardly from said a central recess is formed on the substrate top portion. At least one sidewall portion of the IDC is urged into abutting engagement with the at least one abutment surface on the substrate. Another method prevent solder from causing short circuits between adjacent terminals. A plurality of grooves extending laterally outwardly from a central recessed portion are formed. The plurality of grooves defining a plurality of inwardly projecting fingers. A plurality of contact pads on are formed on a respective plurality of fingers. A solder bead is formed on at least some of the plurality of contact pads. The at least one solder bead is isolated from adjacent solder beads and adjacent terminals.

Abstract: This invention combines a multicore shared memory controller and an asynchronous protocol converting bridge to create a very efficient heterogeneous multi-processor system. After traversing the protocol converting bridge the commands travel through the regular processor port. This allows the interconnect to remain unchanged while having any combination of different processors connected. This invention tightly integrates all of the processors into the same memory controller/interconnect.

Abstract: An asynchronous dual domain bridge is implemented between the cache coherent master and the coherent system interconnect. The bridge has 2 halves, one in each clock/powerdown domain—master and interconnect. The asynchronous bridge is aware of the bus protocols used by each individual processor within the attached subsystem, and can perform the appropriate protocol conversion on each processor's transactions to adapt the transaction to/from the bus protocol used by the interconnect.

Abstract: An integrated circuit is formed by forming an isolation recess in a single crystal substrate which includes silicon, filling the isolation recess with isolation dielectric material, and planarizing the isolation dielectric material to be coplanar with the top surface of the substrate to form a buried isolation layer. A non-selective epitaxial process forms single-crystalline silicon-based semiconductor material on exposed areas of the substrate and polycrystalline or amorphous silicon-based material on the buried isolation layer. A cap layer is formed over the epitaxial silicon-based material, and a radiantly-induced recrystallization process causes the polycrystalline or amorphous silicon-based material to form single-crystalline semiconductor over the buried isolation layer.

Abstract: An LED backlight controller combines global/hybrid and local brightness/dimming control for an LED backlight illuminator with local regions illuminated by associated LED strings. Global/hybrid brightness/dimming control performs hybrid digital modulation control for a predefined lower range of brightness levels, with string current maintained at a substantially constant level associated with a predefined maximum brightness for the lower range (controlling brightness by adjusting digital modulation, such as PWM duty cycle, up to a maximum), and performs hybrid string current control for a predefined higher range of brightness levels (controlling brightness by adjusting string current). Local dimming control is performed by introducing a local digital modulation signal into a hybrid digital modulation control path for the associated string, so that digital modulation for the associated string is a combination of local digital modulation and global/hybrid digital modulation.

Abstract: A circuit includes a phase adjustment capacitor (PAC) coupled to a signal path and configured to adjust a phase of a signal on the signal path. A transistor switch device is coupled in series with the PAC to provide a circuit branch parallel with the signal path. The transistor switch device is configured to selectively open or close the circuit branch of the signal path to enable or disable, respectively, the adjustment of the phase of the signal on the signal path via the PAC. A nonlinear capacitance is coupled to a node interconnecting the PAC and the transistor switch device. The nonlinear capacitance is configured to vary inversely proportional with a capacitance of the transistor switch device with respect to the signal on the signal path and to linearize a total capacitance provided by the circuit branch when the circuit branch is open.

Abstract: A circuit includes an amplifier output stage that includes a high switch and a low switch that generates a pulse width modulated (PWM) output signal to provide a load current to a load in response to a PWM input signal. The circuit includes a high gate drive that drives the high switch with a PWM high drive signal derived from the PWM input signal. This includes a low gate drive that drives the low switch with a PWM low drive signal derived from the PWM input signal. The circuit includes an edge corrector that adjusts at least one of a leading edge and a trailing edge of the PWM input signal to compensate for response time differences with respect to a direction of the load current to the load.

Abstract: Disclosed examples include power modules and fabrication methods therefor in which one or more power device dies include a switching device and a second device die with a circuit component are mounted to a lead frame or other interconnect structure on a substrate structure, and a body structure is formed around portions of the power module providing a first opening to expose a portion of the substrate structure to provide an externally accessible first exposed surface along the top of the power module, and the body structure includes a second opening exposing a portion of the first device die along the bottom of the power module to provide a thermally conductive path to draw heat away from the power device dies.

Abstract: An integrated circuit with non-volatile memory cells shielded from ultraviolet light by a shielding structure compatible with chemical-mechanical processing. The disclosed shielding structure includes a roof structure with sides; along each side are spaced-apart contact posts, each with a width on the order of the wavelength of ultraviolet light to be shielded, and spaced apart by a distance that is also on the order of the wavelength of ultraviolet light to be shielded. The contact posts may be provided in multiple rows, and extending to a diffused region or to a polysilicon ring or both. The multiple rows may be aligned with one another or staggered relative to one another.

Abstract: Systems and methods for a universal Serializer-Deserializer (SerDes) architecture are described. In various implementations, a transceiver may include: a first plurality of data flip-flops coupled to a data lookup circuit of a SerDes interface; a second plurality of data flip-flops coupled to the data lookup circuit; a plurality of latches, each latch of the plurality of latches coupled to a corresponding data flip-flop of the second plurality of data flip-flops; and a plurality of multiplexers coupled to the plurality of latches, to the first plurality of data flip-flops, and to a transmitter circuit.

Abstract: A memory management and protection system that manages memory access requests from a number of requestors. Memory accesses are allowed or disallowed based on the privilege level of the master, usually a CPU originating the request based on a Privilege Identifier that accompanies each memory access request. Deputy masters such as DMA controllers inherit the Privilege Identifier of the originating master. An extended memory controller selects the appropriate set of segment registers based on the Privilege Identifier to insure that the request is compared to and translated by the segment register associated with the master originating the request.