Abstract: A sidewall spacer pullback scheme is implemented in forming a transistor. The scheme, among other things, allows silicide regions of the transistor to be made larger, or rather have a larger surface area. The larger surface area has a lower resistance and thus allows voltages to be applied to the transistor more accurately. The scheme also allows transistors to be made slightly thinner so that the formation of voids in a layer of dielectric material formed over the transistors is mitigated. This mitigates yield loss by facilitating more predictable or otherwise desirable transistor behavior.

Abstract: A semiconductor device comprises a first multi-gate device and a second multi-gate device on a semiconductor substrate. The first multi-gate device comprises a first gate structure and the second multi-gate device comprises a second gate structure. An effective width of the first gate structure is greater than an effective width of the second gate structure.

Abstract: A serial data link (10) includes a transmitter (12) using a differential transmitter cell (20) to transmit data using differential signals and a receiver (14) using a differential receiver cell (22) to receive differential signals. When the transmitter (12) is in a power-down state, the differential signals from the differential transmitter cell (20) are set to an illegal state that is detected by the receiver cell (22). Upon detecting the illegal state, unnecessary circuitry in the receiver (14) is shut off or placed in a low power state to conserve energy. When data transmission resumes, the receiver cell (22) automatically restores power to its circuitry and resumes receiving data.

Abstract: A method and/or a system of at-speed transition fault testing with low speed scan enable is disclosed. In one embodiment, a digital system includes any number of scan chains. Each scan chain may have any number of scan cells, an at-speed local scan enable signal to control a mode of operation, and any number of last transition generator cells. In addition, each last transition generator cell includes a first flip-flop with an output connected to a second flip-flop input, an input multiplexer to apply any one of a first flip-flop output data and an OR gate having a first flip-flop input based on a state of the at-speed local scan enable signal, and an OR gate having a first flip-flop output and the global scan enable signal as inputs to generate the at-speed local scan enable signal based on a state of the global scan enable signal.

Abstract: There is provided a method for Loss of Signal Built In Self Test, and corresponding apparatus comprising: a loopback driver for receiving test signals, and for directing the test signals to at least one of a first output of the loopback driver and a second output of the loopback driver; a Digital to Analogue Converter DAC connected to the loopback driver for controlling the amplitude of the data input signals transmitted by the loopback driver; and coupling means for directing the scaled signals to a Loss of Signal detector.

Abstract: A method of forming a memory device (e.g., a DRAM) including array and peripheral circuitry. A plurality of undoped polysilicon gates 58 are formed. These gates 58 are classed into three groups; namely, first conductivity type peripheral gates 58p, second conductivity type peripheral gates 58n, and array gates 58a. The array gates 58a and the first conductivity type peripheral gates 58n are masked such that the second conductivity type peripheral gates 58p remain unmasked. A plurality of second conductivity type peripheral transistors can then be formed by doping each of the second conductivity type peripheral gates 58p, while simultaneously doping a first and a second source/drain region 84 adjacent each of the second conductivity type peripheral gates 58p. The second conductivity type peripheral gates 58p are then masked such that the first conductivity type peripheral gates 58n remain unmasked.

Abstract: An apparatus for reducing current leakage between an input locus and at least one power rail for a system includes, for each respective power rail: (a) A first diode unit coupled between the input locus and a coupling locus. The first diode unit is configured to effect substantially zero potential drop during normal operation of the apparatus. (b) A second diode unit coupled between the coupling locus and the respective power rail. The second diode unit is configured to present no forward bias during normal operation of the apparatus. The first and second diode units cooperate to effect current flow between the input locus and the respective power rail during a predetermined operational condition of the apparatus.

Abstract: A system and method for amplifier gain measurement and compensation. A method for compensating a signal gain of an amplifier circuit includes determining a desired gain for the amplifier circuit, determining an operating temperature of the amplifier circuit, adjusting a set of signal gains based on the operating temperature to produce a set of adjusted signal gains, determining a desired gain setting based on the desired gain and the set of signal gains, and providing the desired gain setting to the amplifier circuit.

Abstract: A test system in an integrated circuit includes a boundary scan cell. The boundary scan cell includes a first storage element and a second storage element connected in series with the first storage element. The boundary scan cell also includes initialization logic connected between an output of the first storage element and an input of the second storage element. The initialization logic provides the output of the first storage element to the input of the second storage element unchanged during a first operating state, and provides an inverted version of the output of the first storage element to the input of the second storage element during a second operating state.

Abstract: In a method and system for testing, a tester (110) is operable to communicate test signals (124, 126) at a tester clock speed, and a device (190) to be tested is operable to communicate the test signals (124, 126) at a device clock speed, the device clock speed being greater than the tester clock speed. A test module (120) is interposed between the tester (110) and the device (190) to enable data transfer between the tester (110) and the device (190) at their respective clock speeds. The test module (120) includes a memory module (250) capable of storing N samples of the test signals (124, 126) at a selectable one of the tester clock speed and the device clock speed. The memory module (250) is operable to provide the N samples at a selectable one of the tester clock speed and the device clock speed.

Abstract: This invention is an integrated circuit having at least one data pin connecting to external circuits. The invention includes a plurality of operational units each having at least one data input/output for data transfer and an enable input. The operational unit have a normal mode and a stall mode controlled by an enable input. The operational units can exchange data via the data input/output in normal mode and are not capable of exchanging data in the stall mode. A selection logic selectively enables an operation unit and connects the data input/output of the enabled operation unit to the at least one data pin. The selection logic is responsive to external signals on at least one data pin to selectively enable operation units.

Abstract: This invention is an integrated circuit having at least one data pin connecting to external circuits. The invention plural operational units each having a normal mode and a stall mode controlled by an enable input. Selection logic selectively enables an operation unit and connects the data input/output of the enabled operation unit to the data pin. The operational units are responsive to a preceding or following key to enter the normal mode. Each operational unit switches between stall mode and the normal mode upon receiving a corresponding predetermined selection number of pulses at while the clock input receives a non-cycling signal. Greater number of pulses deselect all operational units, switch operational units to the normal mode if the correct key is received and switch all operational units to the stall mode.

Abstract: In a method and system for fabricating a semiconductor device (100) having a package-on-package structure, a base laminate substrate (BLS) (110) is formed to include a base center portion (112) and a peripheral portion (114) separated by a barrier element (120). The barrier element (120) forms a peripheral wall (118) to surround the base center portion (112). A frame shaped top laminate substrate (TLS) (130) is disposed over the peripheral portion (114) of the BLS (110). The TLS (130) has an open top center portion (132) matching the base center portion (112) surrounded by the peripheral wall (118) to form a cavity (140). A plurality of conductive bumps (150) each disposed between a top contact pad (134) of the TLS and a base contact pad (116) of the peripheral portion (114) of the BLS (110) are formed to provide electrical and mechanical coupling therebetween. The barrier element (120) forms a seal between the cavity (140) and the plurality of conductive bumps (150).

Abstract: Disclosed herein is a method of projecting images using reflective light valves. Pixel patterns generated of the light valve pixels based on image data are projected at different locations at a time such that the perceived resolution of the projected images can be higher than the total number of pixels in the light valve.

Abstract: A semiconductor device comprising a leadframe (903), which has first (903a) and second (903b) surfaces, a planar pad (910) of a certain size, and a plurality of non-coplanar members (913) adjoining the pad. The device further has a heat spreader (920) with first (920a) and second (920b) surfaces, a planar pad of a size matching the leadframe pad size, and contours (922), into which the leadframe members are inserted so that the first spreader pad surface touches the second leadframe pad surface across the pad size. A semiconductor chip (904) is mounted on the first leadframe pad surface. Encapsulation material (930), preferably molding compound, covers the chip, but leaves the second spreader surface uncovered.

Abstract: A digital data interface system comprises a data transmitter configured to transmit a data word across a plurality of data lines. The data word can comprise a plurality of digital data bits having a bit number order from a lowest bit number to a highest bit number with the lowest ordered bit numbers having higher noise content and the highest ordered bit numbers having higher harmonic content. The system also comprises an encoder configured to arrange the plurality of digital data bits as serialized data sets to be transmitted over each of the plurality of data lines by the data transmitter with consecutive data bits of at least one serialized data set being matched such that bits with the higher harmonic content are matched with bits of the higher noise content to substantially mitigate of at least one of the noise content and the harmonic content of the data word.

Abstract: A wire bonder (900) with a rigid pedestal (902) having resilient inserts (920). A package (904) placed on the pedestal (902) contains an electrical device (906). The bond pads on the electrical device (906) are electrically connected to bond pads on the package (904) by a series of bond wires (908) through use of a well know bonding process. A vacuum source holds the package (904) against the pedestal (902) deforming the resilient strips (920) located in the rigid member (902) of the pedestal and ensuring good contact between the ground pads of the package (904) and conductive resilient members (920). The resilient members (920) are conductive and electrically connect the package grounds to a system ground (922).

Abstract: The objective of this invention is to provide a boost circuit that reduces power consumption and prevents malfunctioning when the input voltage becomes greater than a target voltage for the output voltage. Control circuit module 5 sets both control signals HCNT2 and LCNT2 to low level “L” when the conditions “output voltage VBoost is higher than voltage OVREF” and “voltage (VIN+VOFFSET) is higher than output voltage VBoost” are satisfied. With this, in boost circuit module 7, switch SWH will be off and switch SWL will be on to forcibly switch to mode B. In mode B, because switch SWH is on, output voltage VBoost will be near input voltage VIN, and the power consumption can be reduced.

Abstract: Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter and a receiver. In one embodiment, the transmitter includes a synchronization unit configured to provide a primary synchronization signal and a secondary synchronization signal having first and second segments. The transmitter also includes a secondary scrambling unit configured to provide a scrambled secondary synchronization signal, wherein scrambling agents for the first and second segments are derived from a primary synchronization sequence of the primary synchronization signal. The secondary scrambling unit is further configured to provide an additional scrambling of one of the first and second segments, wherein a second scrambling agent is derived from the remaining segment of a secondary synchronization sequence of the secondary synchronization signal.

Abstract: An LDO regulator (10) produces an output voltage (Vout) by applying the output voltage to a feedback input (6) of a differential input stage (10A) and applying an output (3) of the differential input stage to a gate of a first follower transistor (MP4) having a source coupled to an input (8) of a class AB output stage (10C) which generates the output voltage. Demanded load current is supplied by the output voltage during a dip in its value to a gate of a second follower transistor (MP5) having a gate coupled to the output of the input stage to decrease current in a current mirror (MN5,6) having an output coupled to a current source (I1) and a gate of an amplifying transistor (MN7). This causes the current source to rapidly turn on the amplifying transistor to cause it to rapidly turn on a cascode transistor (MN3), causing it to turn on a pass transistor (MP3) of the output stage.