Abstract: One aspect of the invention relates to a method for accessing a memory device. One embodiment relates to a method for accessing a memory device. In the method during a read operation, one data value is provided on a local IO line while complimentary local IO line that is associated with the local IO line is inactivated. During a write operation, another data value is provided on the local IO line and a complimentary data value is provided on the complimentary local IO line. Other systems and methods are also disclosed.

Abstract: The present invention provides a microstructure device comprising multiple substrates with the components of the device formed on the substrates. In order to maintain uniformity of the gap between the substrates, a plurality of pillars is provided and distributed in the gap so as to prevent decrease of the gap size. The increase of the gap size can be prevented by bonding the pillars to the components of the microstructure. Alternatively, the increase of the gap size can be prevented by maintaining the pressure inside the gap below the pressure under which the microstructure will be in operation. Electrical contact of the substrates on which the micromirrors and electrodes are formed can be made through many ways, such as electrical contact areas, electrical contact pads and electrical contact springs.

Abstract: Methods and apparatus for power monitoring with sequencing and supervision are disclosed. An example method disclosed herein includes supervising a first power rail and a second power rail, sequencing a first enable signal associated with the first power rail and a second enable signal associated with the second power rail, and determining whether the first power rail is enabled based on regulation information determined while supervising the first power rail.

Abstract: A device with a semiconductor chip assembled on a planar substrate and encapsulation compound surrounding the assembled chip and a portion of the substrate near the chip; the compound has a planar top area. The encapsulation compound has a plurality of side areas reaching from the substrate to the top area; these side areas form edge lines with the top area, where the top area plane intersects with the respective plane of each side area. The encapsulation compound is recessed along the edge lines so that the material is caved-in along the lines; this feature causes the recess to prevent any compound from the side area planes to reach the top area plane, whereby the planarity of the top area is preserved.

Abstract: A method is disclosed for forming a micromechanical device. The method includes fully or partially forming one or more micromechanical structures multiple times on a first substrate. A second substrate is bonded onto the first substrate so as to cover the multiple areas each having one or more micromechanical structures, so as to form a substrate assembly. The substrate assembly is then separated into individual dies, each die having the one or more micromechanical structures held on a portion of the first substrate, with a portion of the second substrate bonded to the first substrate portion. Finally, the second substrate portion is removed from each die to expose the one or more micromechanical structures on the first substrate portion.

Abstract: The present invention facilitates memory devices and operation thereof by employing a repair cache system 600 to correct or repair identified faulty memory locations. The repair cache system 600 includes a decoder that selects local repair location addresses from repair sets 610 according to a repair region address 604. Comparators 616 compare the selected local repair location addresses with a local repair address 606 to identify a match. Repair register banks 622 that comprise a plurality of repair registers are selected if an associated comparator 606 identifies a match. Then, a register within the associated register bank is selected according the repair region address 604 for read/write access. If a match is not identified, a memory location from a main memory 630 is selected for read/write access.

Abstract: This invention is a solid-state image pickup device that solves the problem of limited dynamic range in the high luminance region in an image sensor having white pixels. White pixels or yellow pixels and at least red pixels, green pixels or blue pixels are arranged in array form on the light receiving surface of a semiconductor substrate. White pixels or yellow pixels have an additional capacitance CS connected to the photodiode via the floating diffusion, a capacitance coupling transistor S that can couple or separate the floating diffusion and the additional capacitance. The proportion of white or yellow pixels to the total number of pixels is higher in a central portion of the light receiving surface than a peripheral portion. The white or yellow pixel may share a floating diffusion with a red, green or blue pixel.

Abstract: A LDMOS transistor having a channel region located between an outer boundary of an n-type region and an inner boundary of a p-body region. A width of the LDMOS channel region is less than 80% of a distance between an outer boundary of an n+-type region and the inner boundary of a p-body region. Also, a method for making a LDMOS transistor where the n-type dopants are implanted at an angle that is greater than an angle used to implant the p-type dopants. Furthermore, a VDMOS having first and second channel regions located between an inner boundary of a first and second p-body region and an outer boundary of an n-type region of the first and second p-body regions. The width of the first and second channel regions of the VDMOS is less than 80% of a distance between the inner boundary of the first and second p-body regions and an outer boundary of an n+-type region of the first and second p-body regions.

Abstract: A method of generating a scalable OPC model for composing reticle pattern files from IC layouts using 2D test patterns is disclosed. The 2D test patterns include basic features which replicate features found in advanced ICs. Variations of feature dimensions and structure pitches provide measurement data which enables the scalability of the OPC model. A method of checking reticle pattern files for features which cannot be modeled by the scalable OPC model is also disclosed.

Abstract: An apparatus is provided. The apparatus comprises a digital signal generator, an analog filter, an amplitude modulator, and an analog-to-digital converter (ADC). The digital signal generator has a demodulator and provides a digital excitation signal. The analog filter is coupled to the digital signal generator. The amplitude modulator has a variable capacitor and is coupled to the analog filter. The amplitude modulator also generates an amplitude modulated signal with an amplitude that is a function of the capacitance of the variable capacitor. The ADC is coupled to the amplitude modulator and the demodulator, and the digital signal generator and the demodulator operate synchronously.

Abstract: A circuit and method for determining overcurrent in a FET detects an output voltage of the FET in both a positive and negative polarity. The related positive or negative currents through the FET can be measured to determine whether an overcurrent condition exists. By measuring positive and negative currents in the FET, the overcurrent detector can obtain twice as much information as when measuring a positive current alone, and can respond more readily to overcurrent conditions. The overcurrent detector avoids the constraints typically observed in cycle-by-cycle PWM control with single polarity Vds sensing, while permitting a relaxation in the timing requirements for current sensing. A spike suppression circuit also contributes to longer sensing intervals.

Abstract: A cascaded delta-sigma modulator includes a first stage delta-sigma modulator (10A) having first adder (2) followed by first (3) and second (6) integrators, a second adder (4), and a quantizer (7) the output of which is fed back to the first adder by an A/D (9). A gain circuit (5) is also connected between the first integrator and the second adder. The quantizer output is coupled by interstage circuitry to a second stage converter (100B) having a transfer function represented by the expression OUT(z)=z?nIN(z)+G(z)E2(z). An error cancellation circuit (12) includes inputs coupled to the output of the quantizer and an output of the second stage converter so as to provide a flat transfer function of the cascaded first stage delta-sigma modulator and second stage converter and the error cancellation circuit, despite non-flatness in a transfer function of the first stage delta-sigma modulator.

Abstract: The present invention pertains to semiconductor memory devices, and particularly to a system and method for adaptively setting the operating voltages for SRAM for both Vtrip and SNM to reduce power while maintaining functionality and performance, based on modeling and characterizing a test structure. One embodiment comprises an SRAM array, a test structure that characterizes one or more parameters that are predictive of the SRAM functionality and outputs data of the parameters, a test controller that reads the parameters and identifies an operating voltage that satisfies predetermined yield criteria, and a voltage controller to set an operating voltage for the SRAM array based on the identified operating voltage. One method sets an operating voltage for an SRAM by reading test structure data of the parameters, analyzing the data to identify an operating voltage that satisfies predetermined yield criteria, and setting the operating voltage for the SRAM based on the identified operating voltage.

Abstract: One embodiment of the present invention includes a communication system. The system comprises a communications controller configured to control transmission and reception of communications data in a network. The system also comprises a memory configured to store configuration data associated with the communications controller and application parameters associated with each of a plurality of communications applications. The system further comprises an interface converter interconnecting the communications controller and the memory and configured to convert a first bus interface protocol associated with the communications controller to a second bus interface protocol for providing read and write data transfer of the configuration data and the application parameters between the communications controller and the memory.

Abstract: Various systems and methods for implementing memory devices are disclosed. For example, some embodiments of the present invention provide sub-threshold memory devices that include a differential bit cell. Such a differential bit cell includes two PMOS transistors, two NMOS transistors, and two inverters. The source of the first PMOS transistor and the source of the second PMOS transistor are electrically coupled to a bit line input, and the source of the first NMOS transistor and the source of the second NMOS transistor are electrically coupled to the bit line input. The gate of the first NMOS transistor and the gate of the second NMOS transistor are electrically coupled to a word line input. The gate of the first PMOS transistor and the gate of the second PMOS transistor are electrically coupled to an inverted version of the word line input.

Abstract: An amplifier driver circuit (10) includes first (11-1) and second (11-2) feedback amplifiers including first (14-1) and second (14-2) upper current mirrors, respectively, and first (16-1) and second (16-2) lower current mirrors, respectively, first (12-1) and second (12-2) amplifier input stages receiving a common mode input signal, and first (18-1) and second (18-2) amplifier output stages coupled to outputs of the first and second amplifier input stages, respectively. Each current mirror has an input (IN) and first (OUT1) and second (OUT2) outputs. Upper bias terminals of the first (12-1) and second (12-2) amplifier input stages are coupled to the inputs (IN) of the first (14-1) and second (14-2) upper current mirrors, respectively, and are cross-coupled to the second outputs (OUT2) of the second (16-2) and first (16-1) lower current mirrors, respectively.

Abstract: A circuit assembly for converting a differential input clock signal pair into a single-ended output clock signal comprises a NMOS differential amplifier (20) including two N-channel field-effect transistors (N1, N2) which converts the input clock signal pair (CLK, NCLK) applied to its differential inputs into a first single-ended signal, a PMOS differential amplifier (22) including two P-channel field-effect transistors (P3, P4) which converts the input clock signal pair applied to its differential inputs into a second single-ended signal, a bias circuit (N5, N6, N7, P5, P6) generating for each differential amplifier a bias voltage defining its working point at which said field-effect transistors (N1, N2; P3, P4) change state as a function of said input clock signal pair (CLK, NCLK), and a NAND circuit (32) for linking said first and said second single-ended signal and outputting the single-ended output clock signal (A-CLK) as the result thereof.

Abstract: The present invention facilitates semiconductor fabrication by maintaining shape and density of an etch stop layer (206) during trench fill operations. The shape and density of the etch stop layer (206) is maintained by forming a protective alloy liner layer (310) on the etch stop layer (206) prior to trench fill operations. The protective alloy liner (310) is comprised of an alloy that is resistant to materials employed in the trench fill operations. As a result, clipping and/or damage to the etch stop layer (206) is mitigated thereby facilitating a subsequent planarization process that employs the etch stop layer (206). Additionally, selection of thickness and composition (1706) of the formed protective alloy (310) yields a stress amount and type (1704) that is applied to channel regions of unformed transistor devices, ultimately providing for an improvement in channel mobility.

Abstract: A semiconductor device with an improved solder joint system is described. The solder system includes two copper contact pads connected by a body of solder and the solder is an alloy including tin, silver, and at least one metal from the transition groups IIIA, IVA, VA, VIA, VIIA, and VIIIA of the Periodic Table of the Elements. The solder joint system also includes, between the pads and the solder, layers of intermetallic compounds, which include grains of copper and tin compounds and copper, silver, and tin compounds. The compounds contain the transition metals. The inclusion of the transition metals in the compound grains reduce the compound grains size and prevent grain size increases after the solder joint undergoes repeated solid/liquid/solid cycles.

Abstract: Digital audio circuitry including modulation circuitry (35; 135) for generating a pulse-width modulated (PWM) signal from processed pulse-code modulated (PCM) audio signals. The modulation circuitry includes a duration quantizer function (32) that generates a sequence of duration values d(k) from received PCM samples, quantized to integer multiples of periods of a master PWM clock (CLKpwm). The duration quantizer function also produces a feedback PCM value x(k) from each quantized duration value d(k) that is applied to a loop filter (36), the output of which modifies the received PCM sample stream to suppress quantization noise. Transient effects caused by modulation or abrupt changes in the desired PWM period are suppressed by digitally filtering (34; 134) the PWM period sample stream.