Abstract: A heart monitor includes a single chest accelerometer (210), an analog signal conditioning and sampling section (215) responsive to said accelerometer to produce a digital signal substantially representing acceleration, and a digital processor (220) operable to filter the acceleration signal into a signal affected by body motion and to cancel the body motion signal from the acceleration signal, thereby to produce an acceleration-based cardiac-related signal. Other processes and electronic systems are also disclosed.

Abstract: A method of encoding a set of L bits for transmission on a transmission band through a transmission medium is provided, wherein L is a positive integer that is greater than 1. The method includes: mapping, via a mapping component, the L bits into M symbols; dividing, via a first dividing component, the transmission band into sub-bands; allocating, via an allocating component, the M symbols to individual sub-bands, respectively, for transmission at a first time; and allocating, via the allocating component, the M symbols to different individual sub-bands, respectively, for transmission at a second time.

Abstract: A semiconductor device containing an enhancement mode GaN FET on a III-N layer stack includes a low-doped GaN layer, a barrier layer including aluminum over the low-doped GaN layer, a stressor layer including indium over the barrier layer, and a cap layer including aluminum over the stressor layer. A gate recess extends through the cap layer and the stressor layer, but not through the barrier layer. The semiconductor device is formed by forming the barrier layer with a high temperature MOCVD process, forming the stressor layer with a low temperature MOCVD process and forming the cap layer with a low temperature MOCVD process. The gate recess is formed by a two-step etch process including a first etch step to remove the cap layer, and a second etch step to remove the stressor layer.

Abstract: Described examples include methods of fabricating conductive and resistive structures by direct-write variable impedance patterning using nanoparticle-based metallization layers or chemical reaction-based deposition. In some examples, a low conductivity nanoparticle material is deposited over a surface. The nanoparticle material is selectively illuminated at different applied energy levels via illumination source power adjustments and/or scan rate adjustments for selective patterned sintering to create conductive circuit structures as well as resistive circuit structures including gradient resistive circuit structures having an electrical resistivity profile that varies along the structure length. Further examples include methods in which a non-conductive reactant layer is deposited or patterned, and a second solution is deposited in varying amounts using an additive deposition for reaction with the reactant layer to form controllably conductive structures.

Abstract: Vapor cells and methods for making the same are presented, in which a cell cavity is completely filled with aqueous alkali metal azide solution and the solution is dried at a controlled evaporation rate to substantially maintain edge contact pinning at an interface with the cavity sidewall to promote preferential evaporation in the center and outward capillary flow from an unpinned air-fluid interface toward the sidewall to form crystallized alkali metal material at the sidewall while inhibiting drying of dispersed aqueous solution on a transparent cavity bottom to provide substantially unrestricted passage of light through the cavity for atomic clock and other applications.

Abstract: Described examples include graphene Hall sensors, magnetic sensor systems and methods for sensing a magnetic field using an adjustable gate voltage to adapt the Hall sensor magnetic field sensitivity according to a control input for environmental or process compensation and/or real-time adaptation for balancing power consumption and minimum detectable field performance. The graphene Hall sensor gate voltage can be modulated and the sensor output signal can be demodulated to combat flicker or other low frequency noise. Also, graphene Hall sensors can be provided with capacitive coupled contacts for reliable low impedance AC coupling to instrumentation amplifiers or other circuits using integral capacitance.

Abstract: Described examples include a millimeter wave atomic clock apparatus, chip scale vapor cell, and fabrication method in which a low pressure dipolar molecule gas is provided in a sealed cavity with a conductive interior surface forming a waveguide. Non-conductive apertures provide electromagnetic entrance to, and exit from, the cavity. Conductive coupling structures formed on an outer surface of the vapor cell near the respective non-conductive apertures couple an electromagnetic field to the interior of the cavity for interrogating the vapor cell using a transceiver circuit at a frequency that maximizes the rotational transition absorption of the dipolar molecule gas in the cavity to provide a reference clock signal for atomic clock or other applications.

Abstract: A position estimation method for indoor positioning includes filtering an initial position estimate that includes a corresponding covariance that reflects the quality of the geometry of the reference points and a previous initial position estimate that includes a corresponding covariance that reflects the quality of the geometry of the reference points by a Kalman filter to generate an updated previous position estimate, analyzing the updated previous position estimate to determine if the value is outside of a range, and constraining the updated previous position estimate based on the value being outside of the range.

Abstract: A bipolar ESD protection device includes a substrate having a p-type epi layer thereon including an epi region over an n-buried layer (NBL). An n-type isolation tank (iso tank) includes a deep n+ region and NBL for containing an isolated epi region of the epi region. An NPN transistor and an avalanche diode are formed in the isolated epi region. The NPN transistor includes an emitter within a base having a base contact and the collector is a top portion of NBL. The avalanche diode includes a p-type anode region including an anode contact and an n-type cathode region having a cathode contact. The anode region and base are resistively coupled through the epi region. A ground connection couples the emitter to the anode contact and a strike node connection couples the cathode contact to an n+ isolation contact.

Abstract: An integrated circuit including a trench in the substrate with a high quality trench oxide grown on the sidewalls and the bottom of the trench where the ratio of the thickness of the high quality trench oxide formed on the sidewalls to the thickness formed on the bottom is less than 1.2. An integrated circuit including a trench with high quality oxide is formed by first growing a sacrificial oxide in dilute oxygen at a temperature in the range of 1050° C. to 1250° C., stripping the sacrificial oxide, growing high quality oxide in dilute oxygen plus trans 1,2 dichloroethylene at a temperature in the range of 1050° C. to 1250° C., and annealing the high quality oxide in an inert ambient at a temperature in the range of 1050° C. to 1250° C.

Abstract: A semiconductor device with a deep trench has a dielectric liner formed on sidewalls and a bottom of the deep trench. A pre-etch deposition step of a two-step process forms a protective polymer on an existing top surface of the semiconductor device, and on the dielectric liner proximate to a top surface of the substrate. The pre-etch deposition step does not remove a significant amount of the dielectric liner from the bottom of the deep trench. A main etch step of the two-step process removes the dielectric liner at the bottom of the deep trench while maintaining the protective polymer at the top of the deep trench. The protective polymer is subsequently removed.

Abstract: A stacked optoelectronic packaged device includes a bottom die having a top surface including bottom electrical traces and a light source die coupled to ?1 bottom electrical traces. A first cavity die is on the bottom die. An optics die is on the first cavity die and a second cavity die on the optics die. A mounting substrate is on the second cavity die including top electrical traces. A photodetector die is optically coupled to receive light from the light source. The bottom and top electrical traces are both positioned substantially symmetrically on sides of a mirror plane so that when conducting equal and opposite currents a first magnetic field emanating from the first side and a second magnetic field emanating from the second side cancel one another to provide a reduction in magnetic flux density by more than 50% at one or more die locations on the optics die.

Abstract: A CMOS integrated circuit containing an isolated n-channel DEMOS transistor and an isolated vertical PNP transistor has deep n-type wells and surrounding shallow n-type wells providing isolation from the p-type substrate. The isolated n-channel DEMOS transistor has an upper n-type layer providing an extended drain, and a lower p-type layer isolating the extended drain from the underlying deep n-type well. The isolated vertical PNP transistor has an upper n-type layer providing a base and a lower p-type layer providing a collector. A CMOS integrated circuit having opposite polarities of the transistors may be formed by appropriate reversals in dopant types.

Abstract: A split-gate flash memory cell (cell) includes a semiconductor surface. A first control gate (CG) on a first floating gate (FG) and a second CG on a second floating gate (FG) are on the semiconductor surface. A common source or common drain is between the first and second FG. A first select gate and a second select gate on a select gate dielectric layer is between a first BL source or drain (S/D) and the first FG and between a second BL S/D and the second FG, respectively. The first select gate has a first pocket region that has a first doping distribution different from a second doping distribution in a second pocket region associated with the second select gate which reduces a variation in read current (Ir) for the cell between measuring Ir using the first select gate and measuring Ir using the second select gate.

Abstract: A system and method is disclosed that enables a peripheral or slave device to seamlessly transition in and out of sleep state while remaining completely transparent to host software. When the device is in a sleep mode and incoming data is detected, the device begins a wake-up procedure and data is routed to a first, transitional memory. The size of the transitional memory is selected such that it is capable of buffering data received during time required for the system memory to stabilize from wake-up. Once a second, extended memory is stabilized, the data is buffered from the transitional memory to the extended memory. The device resumes normal operation when its processor has initialized and can read data from the extended memory.

Abstract: Charge to voltage conversion integrator circuitry for data acquisition front-end and other applications to provide a single-ended up a voltage using an input bias capacitance and a switching circuit to selectively place an input transistor in a negative feedback configuration in a first mode to charge the input bias capacitance to a calibration voltage for compensating integrator amplifier bias circuitry, with the switching circuit connecting an input node and the input bias capacitance in a second mode to integrate the input current signal across a feedback capacitance to provide a single-ended output voltage with the input bias capacitance maintaining a zero voltage at the input node.

Abstract: A low power sound recognition sensor is configured to receive an analog signal that may contain a signature sound. The received analog signal is evaluated using a detection portion of the analog section to determine when background noise on the analog signal is exceeded. A feature extraction portion of the analog section is triggered to extract sparse sound parameter information from the analog signal when the background noise is exceeded. An initial truncated portion of the sound parameter information is compared to a truncated sound parameter database stored locally with the sound recognition sensor to detect when there is a likelihood that the expected sound is being received in the analog signal. A trigger signal is generated to trigger classification logic when the likelihood that the expected sound is being received exceeds a threshold value.

Abstract: An apparatus includes a light source to generate source light through an optically transmissive medium to an object. A receiver includes a near zone light sensor and a far zone light sensor positioned on a substrate with the light source. The near zone light sensor is positioned on the substrate to, in response to the generated source light, receive reflected source light from the object and the optically transmissive medium. The far zone light sensor is positioned on the substrate to, in response to the source light, receive the reflected source light from the object and to receive a reduced quantity of the reflected source light from the optically transmissive medium compared to the near zone light sensor.

Abstract: A smart utility network (SUN) device that includes an orthogonal frequency-division multiplexing (OFDM)-based transmitter. The OFDM-based transmitter including a signal processor to convert data from a frequency-domain to a time-domain using an inverse fast Fourier transform (IFFT) and configured to perform a time-domain windowing function based on a Hanning window on OFDM symbols.

Abstract: A laterally diffused MOS (LDMOS) device includes a substrate having a p-epi layer thereon. A p-body region is in the p-epi layer. An ndrift (NDRIFT) region is within the p-body region providing a drain extension region, and a gate dielectric layer is formed over a channel region in the p-body region adjacent to and on respective sides of a junction with the NDRIFT region, and a patterned gate electrode on the gate dielectric. A DWELL region is within the p-body region, sidewall spacers are on sidewalls of the gate electrode, a source region is within the DWELL region, and a drain region is within the NDRIFT region. The p-body region includes a portion being at least one 0.5 ?m wide that has a net p-type doping level above a doping level of the p-epi layer and a net p-type doping profile gradient of at least 5/?m.