Abstract: An apparatus for driving a pulse width modulation reference signal includes: (a) A converting unit receiving an input signal at an input locus and presenting an output current at an output locus. The input signal varies at a first frequency. The output current is substantially related with the first frequency. (b) A capacitive element coupled with the output locus for charging by the output current. The pulse width modulation reference signal is related with voltage across the capacitive element.

Abstract: A method of wireless communication including a plurality of fixed basestations and a plurality of mobile user equipment with each basestation transmitting to any user equipment within a corresponding cell a sounding reference signal sub-frame configuration indicating sub-frames when sounding is permitted. Each user equipment recognizes the sounding reference signal sub-frame configuration and sounds only at permitted sub-frames. Differing cells may have differing sounding reference signal sub-frame configurations. There are numerous manners to encode the transmitted information.

Abstract: In one aspect, a method for configuring a ball grid array is disclosed. The method may include identifying a number of balls for use in a ball grid array, determining a number of rows and a number of columns for the ball grid array, and populating the ball grid array at least in part with a plurality of ball-space groupings. The method may also include allocating an unpopulated portion of an area bounded by the at least one first outside row, the at least one second outside row, the at least one first outside column, and the at least one second outside column, to be free of balls. The method may also include routing a signal line from a ball of at least one ball-space grouping to a space of the at least one ball-space grouping and routing the signal line to a substrate layer through a via.

Abstract: An electronic device compares a first voltage with a selected first reference voltage or second reference voltage. The electronic device includes a comparator having a first input receiving the first voltage, a second input receiving the selected reference voltage and an output providing an output signal based on a comparison. A control stage connected to the output of the comparator generates a control signal based on the output of the comparator. The electronic device selects either the first reference voltage or the second reference voltage in response to the control signal thus comparing the first voltage with the selected reference voltage.

Abstract: An electronic circuit comprising a transistor-based RF (radio frequency) power amplifier (112) having balanced outputs (172, 176), a transistor-based receiver RF amplifier (116) having balanced inputs (152, 156) ohmically connected to said balanced outputs (172, 176) respectively of said RF power amplifier (112), and a balun (114) having a primary (182, 186) and a secondary (188), said primary (182, 186) having primary connections and a supply connection (185) of said primary (182, 186) intermediate said primary connections and said primary connections ohmically connected both to said balanced outputs (172, 176) of said RF power amplifier (112) respectively and to said balanced inputs (152, 156) of said receiver RF amplifier, thereby to switchlessly couple RF between the balun (114) and the RF power amplifier (112) and switchlessly couple RF between the balun (114) and the receiver RF amplifier (116). Other electronic circuits, processes, devices and systems are disclosed.

Abstract: In a first embodiment a TAP of IEEE standard 1149.1 is allowed to commandeer control from a WSP of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface. One approach provides for the TAP to maintain access and control of the TAP instruction register, but provides for a selected data register to be accessed and controlled by either the TAP+ATC or by the discrete CaptureDR, UpdateDR, TransferDR, ShiftDR, and ClockDR WSP data register control signals.

Abstract: A weight level generator is provided. Weight level generator W has plural weight generators 5-1-5-j. At least one of said plural weight generators is used at at least two different time rates. Also, a digital-to-analog converter (DAC) using said weight generators is equipped with a digital signal source, a weight controller, and a weight generator.

Abstract: A mixer 1100 with a plurality of signal paths typically requires separate clock generating hardware for each signal path. However, the redundancy of having multiple clock generating hardware significantly increases power consumption and integrated circuit area when the mixer 1100 is integrated into silicon. A method and apparatus 1125 containing a circuit for generating a set of clock signals that can be shared by the different signal paths is presented. Advantage is taken of the significant capacitance difference between different sampling capacitors in the mixer and the superposition property.

Abstract: An integrated circuit containing an encoder which avoids setup/hold violation in a memory element of one clock domain, when receiving data from another memory element of another clock domain during a scan based testing of an integrated circuit. In an embodiment, the encoder receives a test clock, including a capture pulse during a capture mode of the scan test, but forwards the capture pulse only to one of the clock domains and blocking the capture pulse to other clock domains. As a result, erroneous captures in the memory element receiving data from another clock domain is avoided without the need of closing timing on paths which are not functionally exercised.

Abstract: System and method for enhancing image quality in a display system. A preferred embodiment comprises a variable light source capable of producing a light of specified intensity and color, an array of light modulators optically coupled to the variable light source, the array to modulate the light based upon image data to display images on a display plane, a controller coupled to the array, the controller to issue commands to control the array, and a light driver circuit coupled to the variable light source and the controller, the light driver circuit to provide a signal to the variable light source to specify the intensity of the light produced by the variable light source, when there is a change in a color of light being displayed or when a change in a weight of the image data to be displayed requires less light to be displayed than a current output level.

Abstract: An apparatus for providing active mode power reduction for circuits having data retention includes a master slave flip flop (MSFF) for latching a data input. An output level shifter (OLS), coupled to the MSFF, retains the data input in response to the MSFF being operable in an active power saving mode (APSM) to reduce power. The OLS operating in the APSM provides a level shifter output having a configurable voltage, thereby providing output isolation. A change in an operating mode of the MSFF between an active mode and the APSM is independent of a retention (RET) mode input.

Abstract: A method and system to build a control flow graph by execution of micro-sequences using hardware. Some illustrative embodiments are a processor comprising fetch logic that retrieves an instruction from a memory, the instruction being part of a program, and decode logic coupled to the fetch logic which decodes the instruction, wherein the instruction decoded by the decode logic triggers execution of a micro-sequence to enter the instruction in a control flow graph.

Abstract: Method for removing contaminants from a surface during semiconductor fabrication. A preferred embodiment comprises developing a resist layer on a top surface of a semiconductor substrate, curing the developed resist layer, and cleaning the developed resist layer with a developer solution to remove contaminants. The cleaning makes use of the same developer solution used to develop the resist layer, so the cleaning makes use of a process that already exists and requires no additional investment to implement, while the curing stabilizes the developed resist layer so that the cleaning does not damage the developed resist layer.

Abstract: A LDMOS transistor having a channel region located between an outer boundary of an n-type region and an inner boundary of a p-body region. A width of the LDMOS channel region is less than 80% of a distance between an outer boundary of an n+-type region and the inner boundary of a p-body region. Also, a method for making a LDMOS transistor where the n-type dopants are implanted at an angle that is greater than an angle used to implant the p-type dopants. Furthermore, a VDMOS having first and second channel regions located between an inner boundary of a first and second p-body region and an outer boundary of an n-type region of the first and second p-body regions. The width of the first and second channel regions of the VDMOS is less than 80% of a distance between the inner boundary of the first and second p-body regions and an outer boundary of an n+-type region of the first and second p-body regions.

Abstract: A link configuration unit includes a hybrid bundling module configured to provide a hybrid ACK/NAK bundling structure for an uplink ACK/NAK entity from user equipment, wherein the hybrid ACK/NAK bundling structure corresponds to an uplink-downlink configuration of subframe assignments. Additionally, the link configuration unit also includes a sending module configured to transmit the hybrid ACK/NAK bundling structure to the user equipment.

Abstract: A LDMOS transistor having a channel region located between an outer boundary of an n-type region and an inner boundary of a p-body region. A width of the LDMOS channel region is less than 80% of a distance between an outer boundary of an n+-type region and the inner boundary of a p-body region. Also, a method for making a LDMOS transistor where the n-type dopants are implanted at an angle that is greater than an angle used to implant the p-type dopants. Furthermore, a VDMOS having first and second channel regions located between an inner boundary of a first and second p-body region and an outer boundary of an n-type region of the first and second p-body regions. The width of the first and second channel regions of the VDMOS is less than 80% of a distance between the inner boundary of the first and second p-body regions and an outer boundary of an n+-type region of the first and second p-body regions.

Abstract: The present invention is an electronic device comprising a counter driven by an input clock signal for counting clock cycles and providing a count. A clock signal generating stage provides a first set of phase shifted clock signals having m different phases. The electronic device determines n least significant bits of the count of the counter from the logic states of the first set of m phase shifted clock signals.

Abstract: A routing engine for use with a mounter having a chip selector and a method of routing a chip selector of a mounter. In one embodiment, the routing engine includes: (1) a memory configured to receive and store an electronic wafer map that contains coordinates and characterizations of chips of a particular wafer and (2) a travel path generator associated with the memory and configured to employ a heuristic analysis routine to generate a non-raster travel path for the chip selector to traverse with respect to the particular wafer that is shorter than a serpentine raster travel path.

Abstract: The present invention provides, in one embodiment, a transistor (100). The transistor (100) comprises a doped semiconductor substrate (105) and a gate structure (110) over the semiconductor substrate (105), the gate structure (110) having a gate corner (125). The transistor (100) also includes a drain-extended well (115) surrounded by the doped semiconductor substrate (105). The drain-extended well (115) has an opposite dopant type as the doped semiconductor substrate (105). The drain-extended well (115) also has a low-doped region (145) between high-doped regions (150), wherein an edge of the low-doped region (155) is substantially coincident with a perimeter (140) defined by the gate corner (125). Other embodiments of the present invention include a method of manufacturing a transistor (200) and an integrated circuit (300).

Abstract: An integrated circuit includes a supply voltage controller operable to receive a plurality of control signals and at least one circuit supply voltage and to output at least one variable supply voltage to at least one supply terminal of the integrated circuit The controller is operable to switch the variable supply voltage to a first voltage level when the control signals define a first operation and to a second voltage level different from the first voltage level when the control signals define a second operation. The controller is also operable to float the variable supply voltage to a third voltage level different from the first voltage level when the control signals define a third operation.