Abstract: The problem of the invention is to improve S/N and provide a high-sensitivity imaging device. The CMOS image sensor includes multiple pixels arranged in a two-dimensional array, where each pixel includes a photodiode PD that receives light to produce charge, a capacitance element FD, and a transfer transistor M1 connected between photodiode PD and capacitance element FD, where the capacitance of capacitance element FD is less than the capacitance of photodiode PD. With the drive method, transfer transistor M1 turns on during a predetermined period in a first charge transfer mode after the charge accumulation period is completed; first charge Q1 accumulated on photodiode PD is transferred to capacitance element FD; the charge on capacitance element FD is then reset; transfer transistor M1 turns on during a predetermined period in a second charge transfer mode after reset is completed; and second charge Q2 accumulated on photodiode PD is transferred to transfer element FD.

Abstract: An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15, test data output leads 13, control leads 17 and an external register present, ERP lead 37. A scan register 25 encompasses the intellectual property core and ERP lead 37 carries a signal indicating the presence of the scan register.

Abstract: One embodiment of the present invention includes a system for providing a soft-start for a power regulator comprising a differential transistor pair that receives an input current and conducts a first current through a first transistor and a second current through a second transistor. One of the first and second current changes in response to a change in the other to maintain a sum of the first and second current being substantially equal to the input current. The system also comprises a comparator that provides an output signal based on a comparison of a first input voltage and a second input voltage associated with the first current and the second current, respectively. The system further comprises a current source activated by the output signal to charge a capacitor that increases a soft-start reference voltage associated with control of the power regulator and which controls the change in the other of the first and second current.

Abstract: Inverse discrete cosine transform (type-III DCT), used in video/image and audio coding, is implemented in the form of FFT to lower computational complexity.

Abstract: The present invention provides a single-electron transistor device 100. The device comprises a source 105 and drain 110 located over a substrate 115 and a quantum island 120 situated between the source and drain, to form tunnel junctions 125, 130 between the source and drain. The device further includes a fixed-gate electrode 135 located adjacent the quantum island 120. The fixed-gate electrode has a capacitance associated therewith that varies as a function of an applied voltage to the fixed-gate electrode. The present invention also includes a method of fabricating a single-electron device 300, and a transistor circuit 800 that include a single-electron device 810.

Abstract: A polarity independent differential data transceiver receives a differential voltage signal and outputs a first logic state when the differential voltage signal is in a positive voltage differential range and/or when the differential voltage signal is in a corresponding negative differential voltage range. The differential data transceiver will output a second logic state in response to receiving a voltage differential signal that is in an intermediate differential voltage range near zero between the positive differential voltage range and the corresponding negative differential voltage range.

Abstract: This invention notes various patterns of uplink and downlink communication in a wireless communication system which satisfy the requirement that a user equipment receiving a downlink grant in subframe n needs to transmit response ACK/NAK bits in an uplink subframe n+k, where k>3 and a user equipment receiving a DL grant or ACK/NAK on physical hybrid automatic repeat request channel (PHICH) in subframe n needs to transmit or retransit UL data bits in an uplink (UL) subframe n+k, where k>3.

Abstract: One embodiment of the present invention relates to a method by which the imprint of a ferroelectric random access memory (FRAM) array is reduced. The method begins when an event that will cause imprint to the memory array is anticipated by an external agent to the device comprising the chip. The external agent sends a command to the control circuitry that the data states are to be written to a particular data state. Upon receiving a signal the control circuitry writes all of the ferroelectric memory cells in the FRAM array to a preferred memory data state. The memory data states are held in the preferred data state for the entire duration of the event to minimize imprint of the FRAM memory cells. When the event ends the external agent sends a command to the control circuitry to resume normal memory operation. Other methods and circuits are also disclosed.

Abstract: An audience and speaker interactive communications system is described. In one embodiment, it includes a server coupled to a loudspeaker, which server includes an application module for receiving and decoding speech samples and transmitting the speech samples to a loudspeaker over an unlicensed wireless communication frequency spectrum. The system also includes a mobile communications device with a connectivity application for gaining access to the server over an unlicensed wireless communication frequency spectrum as well as a client application module for encoding and transmitting speech samples to the server.

Abstract: A process of forming a semiconductor process fabricated device which contains a trench, hole or gap filled with a conformally deposited material is disclosed. A sacrificial planarizing layer is formed on the fill material, and the device is planarized using a selective RIE process which etches the fill material faster than the sacrificial planarizing layer. An overetch step completes the planarization process.

Abstract: A transceiver and a method of controlling aberrant transceiver operation. In one embodiment, the transceiver includes: (1) a processor, (2) an interrupt system coupled to the processor and having a flag register associated therewith, (3) detection circuits associated with corresponding functional units of the transceiver and configured to detect conditions regarding the corresponding functional units and set corresponding flags in the flag register, the interrupt system configured to assert interrupts in response thereto and (4) an interrupt-handing routine executable in the processor and configured to respond to the interrupts by carrying out at least one of loading parameters and generating warnings based on identities of the flags.

Abstract: A semiconductor device that attenuates light to the circuit element area is provided. The semiconductor device includes light-sensitive element area formed on substrate and a circuit element area formed on the substrate. Additionally, a multilayer wiring area is formed on circuit element area. A Tantalum film (which is generally made of tantalum or a tantalum compound) is formed on the surface of the multilayer wiring area to attenuate incident light on circuit element area.

Abstract: A method of wireless communication including a plurality of fixed base stations and a plurality of mobile user equipment with each base station transmitting to any user equipment within a corresponding cell a sounding reference signal sub-frame configuration indicating sub-frames when sounding is permitted. Each user equipment recognizes the sounding reference signal sub-frame configuration and sounds only at permitted sub-frames. Differing cells may have differing sounding reference signal sub-frame configurations. There are numerous manners to encode the transmitted information.

Abstract: The objective of this invention is to provide a test device that can perform a variety of function tests with a relatively simple constitution. The test device is for testing semiconductor device 1, which contains input terminal IN, output terminal OUT and control terminal CTRL, and whose output terminal is in the high-impedance state corresponding to the control signal applied to control terminal CTRL. The test device comprises test signal supply circuit 20, comparator 30 that compares the output signal from the output terminal with a reference voltage, reference voltage setting part 40 that sets the reference voltage to the voltage on the high-level side or on the low-level side, and load voltage supply circuit 50 that applies the load voltage to the output signal when the control signal is input.

Abstract: Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure (106, 306, 400, 404) and the required current density throughput of an electrical contact structure (108, 308, 402, 406) are determined. A required electrical contact area is determined based on the required current density, and the electrical contact structure is then designed to minimize the required electrical contact area with respect to the emitter structure area.

Abstract: The disclosure herein pertains to fashioning an n channel junction field effect transistor (NJFET) and/or a p channel junction field effect transistor (PJFET) with an open drain, where the open drain allows the transistors to operate at higher voltages before experiencing gate leakage current. The open drain allows the voltage to be increased several fold without increasing the size of the transistors. Opening the drain essentially spreads equipotential lines of respective electric fields developed at the drains of the devices so that the local electric fields, and hence the impact ionization rates are reduced to redirect current below the surface of the transistors.

Abstract: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

Abstract: This invention provides the correct Viterbi decode traceback starting index is obtained for all constraint lengths and frame sizes. Reverse transpose operations that depend on the last active add-compare-select unit a cascade block of the state metric update process. This last active add-compare-select unit controls selection of T counter signals used in the decode.

Abstract: A method of manufacturing a semiconductor device that includes forming a gate dielectric layer over a semiconductor substrate. A gate electrode is formed over the gate dielectric layer. A dopant is implanted into an extension region of the substrate, with an amount of the dopant remaining in a dielectric layer adjacent the gate electrode. The substrate is annealed at a temperature of about 1000° C. or greater to cause at least a portion of the amount of the dopant to diffuse into the semiconductor substrate.

Abstract: A method for reducing wafer backside large particle contamination, comprising: performing front end of line processing of a memory device, depositing a thick oxide on the wafer backside so that at least pre-selected oxide thickness remains after back end of line processing is complete and performing the back end of line processing of the memory device.