Patents Assigned to Texas Instruments
  • Patent number: 9443737
    Abstract: Metal contact openings are etched in the barrier layer of a group III-N HEMT with a first gas combination that etches down into the barrier layer, and a second gas combination that etches further down into the barrier layer to a depth that lies above the top surface of a channel layer that touches and lies below the barrier layer.
    Type: Grant
    Filed: April 3, 2013
    Date of Patent: September 13, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yoshikazu Kondo, Shoji Wada, Hiroshi Yamasaki, Masahiro Iwamoto
  • Patent number: 9442162
    Abstract: The disclosure describes a novel method and apparatus for making device TAPs addressable to allow device TAPs to be accessed in a parallel arrangement without the need for having a unique TMS signal for each device TAP in the arrangement. According to the disclosure, device TAPs are addressed by inputting an address on the TDI input of devices on the falling edge of TCK. An address circuit within the device is associated with the device's TAP and responds to the address input to either enable or disable access of the device's TAP.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: September 13, 2016
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 9444494
    Abstract: A network coding method includes receiving a plurality of input packets each having a packet length. Encoding the plurality of input packets by applying a convolutional code across symbols in corresponding positions of the plurality of input packets obtaining a number of encoded packets. The number of encoded packets obtained being more than the number of input packets.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: September 13, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Samantha Rose Summerson, Anuj Batra, June Chul Roh
  • Patent number: 9444481
    Abstract: An analog to digital converter includes an analog input and a voltage comparator coupled to the analog input for comparing a voltage at the analog input to a digitally synthesized waveform. A digital to analog converter (DAC) generates the digitally synthesized waveform. The DAC includes a plurality of capacitors selectively connected in parallel wherein the period between the selection of capacitors is less than the settling time of the voltage across the capacitors.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: September 13, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Dinesh Jain
  • Patent number: 9445405
    Abstract: In at least some embodiments, a wireless networking system is provided. The wireless networking system includes a base-station and a plurality of user devices in communication with the base-station. The base-station selectively assigns each user device to one of a first group and a second group. Also, the base-station selectively assigns each user device to an uplink synchronized state and an uplink non-synchronized state. The base-station allocates a unique reduced identifier to each user device in the uplink synchronized state, but does not allocate unique reduced identifiers to user devices in the non-synchronized state.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: September 13, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Pierre Bertrand, Shantanu Kangude
  • Patent number: 9444478
    Abstract: A voltage regulation system provides a relatively stable voltage source without introducing the typical costs of a ground buffer. The disclosed voltage regulation system includes a voltage regulator that is operative to detect a change of the load current and regulate a current bypass mechanism to stabilize a total supply current. For example, the voltage regulator includes a current sensor and a current compensation circuit. The current sensor is configure to generate a current compensation signal based on the load current change, whereas the current compensation circuit is configured to adjust a bypass current in response to the current compensation signal. As a result, the bypass current dynamically compensates the load current change such that the ground voltage of a variable load becomes relatively stable over a range of load currents.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: September 13, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mark Allan Shill, Binan Wang
  • Publication number: 20160260454
    Abstract: A hard disk drive write driver system, method and integrated circuit that provides a configurable overshoot current that is based on the length of a pattern in the write current signal being written to the hard disk by the write driver. The hard disk write driver adds a first overshoot current to all patterns in the write current signal and adds an additional second overshoot current to patterns in the write current signal shorter than a first duration. The hard disk drive write driver utilizes a timing component to generate a timed pulse of the first duration and utilize the timed pulse to detect patterns in the write current signal shorter than the first duration. The hard disk drive write driver may be further configured to add the second additional overshoot current to the write current signal if the frequency of the write current signal is above a specified threshold.
    Type: Application
    Filed: December 18, 2015
    Publication date: September 8, 2016
    Applicant: Texas Instruments Incorporated
    Inventor: Marius V. Dina
  • Publication number: 20160260455
    Abstract: A hard disk drive write drive method and integrated circuit that provide a configurable overshoot current based on the length of the pattern in the write current signal that is being written to the hard disk by the write driver. The hard disk write driver adds a first overshoot current to all patterns in the write current signal and adds an additional second overshoot current to patterns in the write current signal shorter than a first duration. The hard disk drive write driver utilizes an H-bridge circuit configured to add the first overshoot current and the additional second overshoot current to the write current signal. The H-bridge circuit is comprised of four switching elements that are configured to generate a first overshoot current for all pattern transitions of the write current signal and generate a second overshoot current for pattern transitions shorter than the first duration.
    Type: Application
    Filed: December 18, 2015
    Publication date: September 8, 2016
    Applicant: Texas Instruments Incorporated
    Inventor: Marius V. Dina
  • Patent number: 9438304
    Abstract: A symbol modulation system applicable to a body area network is disclosed herein. The symbol modulation system includes a symbol mapper. The symbol mapper is configured to determine a time within a predetermined symbol transmission interval at which a transmission representative of the symbol will occur. The time is determined based on a value of a symbol and a value of a time-hopping sequence. The time is selected from a plurality of symbol value based time slots, and a plurality of time-hopping sequence sub-time-slots within each symbol value based time slot. The symbol mapper is configured to generate a single guard interval within the symbol transmission interval. The single guard interval is positioned to terminate the symbol transmission interval.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: September 6, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: June Chul Roh, Anuj Batra, Sudipto Chakraborty, Srinath Hosur
  • Patent number: 9435859
    Abstract: The disclosure describes a novel method and apparatus for improving interposers that connected stacked die assemblies to system substrates. The improvement includes the addition of IEEE 1149.1 circuitry within interposers to allow simplifying interconnect testing of digital and analog signal connections between the interposer and system substrate it is attached too. The improvement also includes the additional 1149.1 controlled circuitry that allows real time monitoring of voltage supply and ground buses in the interposer. The improvement also includes the additional of 1149.1 controlled circuitry that allows real time monitoring of functional digital and analog input and output signals in the interposer. The improvement also provides the ability to selectively serially link the 1149.1 circuitry in the interposer with 1149.1 circuitry in the die of the stack.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: September 6, 2016
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 9438310
    Abstract: Embodiments of the invention provide multiple cyclic prefix lengths for either both the data-payload and frame control header or only the data payload. Frame control header (FCH) and data symbols have an associated cyclic prefix. A table is transmitted in the FCH symbols, which includes a cyclic prefix field to identify the cyclic prefix length used in the data payload. A receiver may know the cyclic prefix length used in the FCH symbols in one embodiment. In other embodiments, the receiver does not know the FCH cyclic prefix length and, therefore, attempts to decode the FCH symbols using different possible cyclic prefix lengths until the FCH symbols are successfully decoded.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: September 6, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Tarkesh Pande, Anand G. Dabak, Il-Han Kim
  • Patent number: 9438335
    Abstract: An optical data transmitter is operable to transmit data other than test data on an optical fiber at a first wavelength and an optical time domain reflectometer is operable to receive data from the optical fiber at the first wavelength and to use the received data at the first wavelength to determine whether a defect exists in the optical fiber.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: September 6, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Nagarajan Viswanathan
  • Patent number: 9436617
    Abstract: A global navigation satellite system (GNSS) includes an efficient memory sharing architecture that provides additional search capacity by, e.g., sharing a portion of GNSS receiver processor memory with a general processor. A memory management unit dynamically revectors memory accesses in accordance with the various states of the GNSS receiver processor and arranging the available memory as a shared memory bank that can be efficiently shared between the general processor and the GNSS receiver processor. An optional ancillary memory system can provide additional memory to the general processor when the GNSS receiver processor has allocated memory that the general processor would otherwise use.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: September 6, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hemanth Mullur Srikantaiah, Sankar Prasad Debnath, Kalpana Suryawanshi
  • Patent number: 9439220
    Abstract: A contactless system is described in which multiple execution environments may be coupled to a near field communication (NFC) controller, wherein each execution environment is configured to communicate with remote readers via the NFC controller using an assigned one of a plurality of communication protocols. During a polling session from a proximate reader, responding to a request command using a requested communication protocol and activating one of the plurality of execution environments assigned to the requested communication protocol to use the NFC controller. An arbitration is performed in response to each polling session such that a same combination of communication protocol and execution environment is not activated for adjacent polling sessions.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: September 6, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Koby Levy, Ran Katz, Tally Mane, Rachel Stahl
  • Patent number: 9438266
    Abstract: A direct current (“DC”) calibration reference voltage is applied at an input terminal of an N-level sigma-delta analog-to-digital converter (“ADC”). The ADC includes a current-mode DAC (“I-DAC”) operating as a feedback element. A count of logical 1s associated with each of N output levels is taken at outputs of a modulator portion of the ADC during a first mismatch measurement interval. Mismatch measurement logic subsequently transposes pairs of current sources between level selection switch matrices. Doing so causes modulator output error components resulting from mismatches between I-DAC current sources (“delta”) to appear as differential level-specific output counts. The mismatch measurement logic compares the differential counts to determine values of delta. The ADC then factors decimated modulator output counts by values of delta in order to correct for the I-DAC current source mismatch(es).
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: September 6, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Krishnaswamy Nagaraj, Manish Goel, Xiao Pu, Hun-Seok Kim
  • Patent number: 9438253
    Abstract: A current mode logic (CML) latch that includes a first transistor coupled to a second transistor, a third transistor coupled to a fourth transistor, a first capacitor connected to the first, second, third, and fourth transistors, and a second capacitor cross-coupled with the first capacitor and connected to the third and fourth transistors. The first and second transistors are configured to receive a data signal. The third and fourth transistors are configured to receive a clock signal.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: September 6, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Mustafa Ulvi Erdogan
  • Patent number: 9436291
    Abstract: In response to a user selecting a key on a keyboard in a first manner, a first alphanumeric character is displayed on a display device. In response to the user selecting the key on the keyboard in a second manner, a virtual key of a diacritic is displayed on the display device. In response to the user selecting the virtual key of the diacritic on the display device, the diacritic is displayed at a location of a second alphanumeric character on the display device.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: September 6, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Sajjad Mahmood Khan
  • Patent number: 9435860
    Abstract: Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: September 6, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Lee D. Whetsel
  • Patent number: 9437449
    Abstract: An integrated circuit may be formed by forming a sacrificial silicon nitride feature. At least a portion of the sacrificial silicon nitride feature may be removed by placing the integrated circuit in a two-step oxidized layer etch tool and removing a surface layer of oxidized silicon from the sacrificial silicon nitride feature using a two-step etch process. The two-step etch process exposes the integrated circuits to reactants from a plasma source at a temperature less than 40° C. and subsequently heating the integrated circuit to 80° C. to 120° C. while in the two-step oxidized layer etch tool. While the integrated circuit is in the two-step oxidized layer etch tool, without exposing the integrated circuit to an ambient containing more than 1 torr of oxygen, at least a portion of the sacrificial silicon nitride feature is removed using fluorine-containing etch reagents, substantially free of ammonia.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: September 6, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Tom Lii, David Farber
  • Patent number: 9437171
    Abstract: A method of local tone mapping of a high dynamic range (HDR) image is provided that includes dividing a luminance image of the HDR image into overlapping blocks and computing a local tone curve for each block, computing a tone mapped value for each pixel of the luminance image as a weighted sum of values computed by applying local tone curves of neighboring blocks to the pixel value, computing a gain for each pixel as a ratio of the tone mapped value to the value of the pixel, and applying the gains to corresponding pixels in the HDR image. A weight for each value is computed based on distance from the pixel to the center point of the block having the local tone curve applied to compute the value and the intensity difference between the value of the pixel and the block mean pixel value.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: September 6, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rajesh Narasimha, Aziz Umit Batur