Abstract: Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.

Abstract: A system for managing energy stored in a plurality of series connected energy storage units has a plurality of energy storage unit controllers, each controller being associated with one of the plurality of energy storage units, a balancing circuit between two of the energy storage units, the balancing circuit being controlled by at least one of the energy storage unit controllers, a serial electrical interface between the energy storage unit controllers for providing voltage isolated bi-directional communication, and a central controller in electrical communication with the energy storage unit controllers.

Abstract: A method of wireless communication including a plurality of fixed basestations and a plurality of mobile user equipment with each basestation transmitting to any user equipment within a corresponding cell a sounding reference signal sub-frame configuration indicating sub-frames when sounding is permitted. Each user equipment recognizes the sounding reference signal sub-frame configuration and sounds only at permitted sub-frames. Differing user equipment may have differing sounding reference signal sub-frame configurations. There are numerous manners to encode the transmitted information.

Abstract: An optical system and method of increasing the contrast of a projected image. The optical system (1800) comprises a combination of aperture stops (1810, 1812) in at least one of the illumination and projection paths to filter scattered light and/or light prone to scatter into the projection aperture.

Abstract: Systems and methods for providing a battery module 110 with secure identity information and authentication of the identity of the battery 110 by a host 120. In one embodiment, the system for providing a battery module with secure identity information includes: (1) a tamper resistant processing environment 200 located within the battery module 110 and (2) a key generator configured to generate a key based on an identity of the battery module 110 and cause the key to be stored within the tamper resistant processing environment 200.

Abstract: In a method and system for fabricating a thermally enhanced semiconductor device (200, 300) is packaged as a through hole single inline package (SIP). A leadframe (210, 310, 410) having a die pad (220, 320, 420) to attach an IC die (230, 330), a first plurality of conductive leads (240, 340, 430) formed from a first portion of metal sheet (432), and a second portion of metal sheet (440) disposed on an opposite side of the IC die (230, 330) as the first plurality of conductive leads is stamped from a metal sheet. The first plurality of conductive leads (240, 340, 430) are arranged in a single line and are capable of being through hole mounted in accordance with the SIP. The second portion of metal sheet (440) includes the die pad (420) to form a heat spreader (260, 360) in the form of the metal sheet. The heat spreader (260, 360) provides heat dissipating for the heat generated by the IC die (230, 330).

Abstract: According to various illustrative embodiments of the present invention, a device for an integrated circuit includes a monolithic frame having a plurality of alignment features disposed thereon, the monolithic frame having a mounting surface disposed thereon for the integrated circuit, the monolithic frame also having a thermal interface area disposed thereon for the integrated circuit. The device also includes an electrical interface capable of providing an electrical connection for the integrated circuit, the plurality of alignment features being substantially independent of the electrical interface, and an adhesive layer disposed between the monolithic frame and the electrical interface.

Abstract: Exemplary embodiments provide structures for dual work function metal gate electrodes. The work function value of a metal gate electrode can be increased and/or decreased by disposing various electronegative species and/or electropositive species at the metal/dielectric interface to control interface dipoles. In an exemplary embodiment, various electronegative species can be disposed at the metal/dielectric interface to increase the work function value of the metal, which can be used for a PMOS metal gate electrode in a dual work function gated device. Various electropositive species can be disposed at the metal/dielectric interface to decrease the work function value of the metal, which can be used for an NMOS metal gate electrode in the dual work function gated device.

Abstract: Methods to implement low cost, high efficiency, low loss power combiner with novel matching circuits are disclosed. A narrow band power combiner enables a high power and high efficiency radio frequency power amplifier to be realized using multiple low voltage CMOS transistors or micro power amplifiers. The power combiner may be printed on a package substrate and realized either using single layer substrate through edge coupling or multiple layers substrate through broadside coupling. The micro power amplifiers may be fabricated using low voltage CMOS technology and electrical connections between the outputs from the micro power amplifiers and the power combiner may be provided through stud bumps in a flip chip technology. With the tunable matching circuits, the present invention allows the narrow band power combiner to be tuned to different frequencies.

Abstract: First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an input circuit and a differential output driver connected to the single pair of LVDS signal paths. An input to the input circuit is also connected to the input of the driver. The input circuit may also receive an offset voltage. In response to its inputs, the input circuit in each device can use comparators, gates and a multiplexer to determine the logic state being transmitted over the pair of LVDS signal paths from the other device. This advantageously reduces the number of required interconnects between the first and second devices by one half.

Abstract: There is presented a method of forming a semiconductor device. The method comprises forming gate structures including forming gate electrodes over a semiconductor substrate and forming spacers adjacent the gate electrodes. Source/drains are formed adjacent the gate structures, and a laminated stress layer is formed over the gate structure and the semiconductor substrate. The formation of the laminated stress layer includes cycling a deposition process to form a first stress layer over the gate structures and the semiconductor substrate and at least a second stress layer over the first stress layer. After the laminated layer is formed, it is subjected to an anneal process conducted at a temperature of about 900° C. or greater.

Abstract: The trace logic are separate from the clocks that operate the system logic. This allows the chip to be placed in a special mode where the functional logic is issued one clock. One frame of trace data is generated for each functional clock issued. A valid signal may be implemented changing state when new information is generated. The trace logic, whose clock is free running, detects the change in state in the valid signal. It then processes the trace information presented to it, exporting this information to a trace recorder. When transmission of this information has created sufficient space to accept a new frame of trace information, the empty signal is generated. This causes the clock generation logic to issue another clock to the system logic.

Abstract: A method of laying out traces for connection of bond pads of a semiconductor chip to a printed wiring board or the like and the layout. There is provided a substrate having top and bottom surfaces with a plurality of rows and columns of vias extending therethrough from the top surface to the bottom surface and having a solder ball secured at the surface of each via. A plurality of pairs of traces is provided on the top surface, each trace of each pair of traces extending to a different one of the vias and extending to vias on a plurality of rows and columns, each of the traces of each pair being spaced from the other trace by a ball pitch, being maximized for identity in length and being maximized for parallelism and spacing. Each of the traces of a pair is preferably further maximized for identity in cross-sectional geometry. A differential signal pair is preferably applied to at least one of a pair of traces.

Abstract: One aspect of the invention provides an integrated circuit(IC) [400b]. The IC comprises transistors [410b] and contact fuses [422b]. The contact fuses each comprise a conducting layer [424b], a frustum-shaped contact [426b] has a narrower end that contacts the conducting layer and a first metal layer [427b] that is located over the conducting layer. A wider end of the frustum-shaped contact contacts the first metal layer. The frustum-shaped contact has a ratio of an opening of the wider end to the narrower end that is at least about 1.2. The contact fuses each further include a heat sink [432b] that is located over and contacts the first metal layer.

Abstract: A mobile communication system is designed with an input circuit coupled to receive a first plurality of signals (rj(i+?j), i=0?N?1) during a first time (T0-T1) from an external source and coupled to receive a second plurality of signals (rj(i+?j), i=N?2N?1) during a second time (T1T2) from the external source. The input circuit receives each of the first and second plurality of signals along respective first and second paths (j). The input circuit produces a first input signal (Rj1) and a second input signal (Rj2) from the respective first and second plurality of signals. A correction circuit is coupled to receive a first estimate signal (?j1), a second estimate signal (?j2) and the first and second input signals. The correction circuit produces a first symbol estimate ({tilde over (S)}1) in response to the first and second estimate signals and the first and second input signals.

Abstract: A process (200) for making integrated circuits with a gate, uses a doped precursor (124, 126N and/or 126P) on barrier material (118) on gate dielectric (116). The process (200) involves totally consuming (271) the doped precursor (124, 126N and/or 126P) thereby driving dopants (126N and/or 126P) from the doped precursor (124) into the barrier material (118). An integrated circuit has a gate dielectric (116), a doped metallic barrier material (118, 126N and/or 126P) on the gate dielectric (116), and metal silicide (180) on the metallic barrier material (118). Other integrated circuits, transistors, systems and processes of manufacture are disclosed.

Abstract: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS. 41-49, provides for selectively using either the 5 signal interface of FIG. 41 or the 3 signal interface of FIG. 8.

Abstract: A data processing apparatus includes a register file and a plurality of functional units. At least one and not all the plurality of the functional units is a critical functional unit. Each critical functional unit supplies its output to a pipeline register. A comparator and multiplexer select a register input for each functional unit or the output of a corresponding pipeline register dependent. In the preferred embodiment, each critical functional unit has a throughput delay time longer than the average of throughput delay times of all functional units.

Abstract: An integrated circuit (25) formed at a semiconducting surface of a substrate including a common p-layer (38) includes functional circuitry (24) formed on the p-layer (38) including a plurality of terminals (IN, OUT, I/O) coupled to the functional circuitry (24). At least one ESD protection cell (30; in more detail 200) is connected to at least one of the plurality of terminals of the functional circuitry (24). The protection cell includes at least a first Nwell (37) formed in the p-layer (38), a p-doped diffusion (36) within the first Nwell (37) to form at least one Nwell diode comprising an anode (37) and a cathode (36). An NMOS transistor 200 is formed in or on the p-layer (38) comprising a n+ source (43), n+ drain (44) and a channel region comprising a p-region (41) between the source and drain, and a gate electrode (45) on a gate dielectric (46) on the channel region.

Abstract: A transmitter includes a bandwidth configuration unit configured to provide an increased system bandwidth corresponding to a bandwidth extension over multiple component carriers. Additionally, the transmitter also includes a transmit unit configured to employ the bandwidth extension.