Abstract: An integrated circuit containing CMOS transistors and an embedded thermoelectric device may be formed by forming active areas which provide transistor active areas for an NMOS transistor and a PMOS transistor of the CMOS transistors and provide n-type thermoelectric elements and p-type thermoelectric elements of the embedded thermoelectric device. Stretch contacts with lateral aspect ratios greater than 4:1 are formed over the n-type thermoelectric elements and p-type thermoelectric elements to provide electrical and thermal connections through metal interconnects to a thermal node of the embedded thermoelectric device. The stretch contacts are formed by forming contact trenches in a dielectric layer, filling the contact trenches with contact metal and subsequently removing the contact metal from over the dielectric layer. The stretch contacts are formed concurrently with contacts to the NMOS and PMOS transistors.

Abstract: Example embodiments of the systems and methods of polyphase generation involve quadrature generation in high frequency digital transceivers. An oscillation signal is received and converted to complex variables with lead and lag phase rotation while performing compensation and calibration due to non-idealities of the in-phase and quadrature phase component parts. In addition to orthagonalizating, the quadrature generator also provides signal amplification and filtering. The quadrature phase generation scheme may be extended to odd harmonics of the fundamental frequency at the input.

Abstract: A secure demand paging system (1020) includes a processor (1030) operable for executing instructions, an internal memory (1034) for a first page in a first virtual machine context, an external memory (1024) for a second page in a second virtual machine context, and a security circuit (1038) coupled to the processor (1030) and to the internal memory (1034) for maintaining the first page secure in the internal memory (1034).

Abstract: Apparatus (and related methods) for a power line communication network include a processor configured to receive beacons over a communication interface. The processor determines a link quality indicator (LQI) for each received beacon and ignores the beacons for at most a predetermined maximum number of beacon receptions when each LQI is below a threshold. The processor responds to a received beacon if the LQI for such received beacon exceeds the threshold or if a predetermined maximum number of beacons have been received with LQIs below the threshold.

Abstract: An integrated circuit containing CMOS transistors and an embedded thermoelectric device may be formed by forming field oxide in isolation trenches to isolate the CMOS transistors and thermoelectric elements of the embedded thermoelectric device. N-type dopants are implanted into the substrate to provide at least 1×1018 cm?3 n-type dopants in n-type thermoelectric elements and the substrate under the field oxide between the n-type thermoelectric elements. P-type dopants are implanted into the substrate to provide at least 1×1018 cm?3 p-type dopants in p-type thermoelectric elements and the substrate under the field oxide between the p-type thermoelectric elements. The n-type dopants and p-type dopants may be implanted before the field oxide are formed, after the isolation trenches for the field oxide are formed and before dielectric material is formed in the isolation trenches, and/or after the field oxide is formed.

Abstract: A system and method for web-based interface design tool is provided. The design tool enables system designers to quickly and independently design a custom serial-link interface. The system provides interface selection and signal integrity analysis. An interface selection may interact with system designers to prompt for a set of selection criteria such as data-rate, supply rail, standard protocol, and intended application. An intelligent search engine screens through a large interface products database based on the selection criteria and provides designers with a list of devices that potentially meet the design criteria. The performance of the custom system with the selected device can be evaluated by using a web-based IBIS-AMI standard-compliant signal integrity simulator. A designers can have options to manually fine tune selected devices' parameters to iterate through different settings to determine the robustness of the solution.

Abstract: A semiconductor device contains an LDNMOS transistor with a lateral n-type drain drift region and a p-type RESURF region over the drain drift region. The RESURF region extends to a top surface of a substrate of the semiconductor device. The semiconductor device includes a shunt which is electrically coupled between the RESURF region and a low voltage node of the LDNMOS transistor. The shunt may be a p-type implanted layer in the substrate between the RESURF layer and a body of the LDNMOS transistor, and may be implanted concurrently with the RESURF layer. The shunt may be through an opening in the drain drift region from the RESURF layer to the substrate under the drain drift region. The shunt may be include metal interconnect elements including contacts and metal interconnect lines.

Abstract: A system and method for a decay lock loop for time varying current regulation in electric motors determines if a predetermined electrical current regulation level for an electric motor has been obtained within a tuning control time window. A coarse control loop increases or decreases a fast current decay, in response to a determination that the predetermined electrical current regulation level has not been obtained within the tuning control time window, until the predetermined electrical current regulation level falls within the tuning control time window. A fine control loop increments or decrements an amount of fast current decay during a total decay time, in response to a determination that the predetermined electrical current regulation level has been obtained within the tuning control time window, until a predetermined timing of the predetermined electrical current regulation level has been obtained.

Abstract: An integrated circuit containing metal replacement gates may be formed by forming a nitrogen-rich titanium-based barrier between a high-k gate dielectric layer and a metal work function layer of a PMOS transistor. The nitrogen-rich titanium-based barrier is less than 1 nanometer thick and has an atomic ratio of titanium to nitrogen of less than 43:57. The nitrogen-rich titanium-based barrier may be formed by forming a titanium based layer over the gate dielectric layer and subsequently adding nitrogen to the titanium based layer. The metal work function layer is formed over the nitrogen-rich titanium-based barrier.

Abstract: A multi-finger lateral high voltage transistors (MFLHVT) includes a substrate doped a first dopant type, a well doped a second dopant type, and a buried drift layer (BDL) doped first type having a diluted BDL portion (DBDL) including dilution stripes. A semiconductor surface doped the second type is on the BDL. Dielectric isolation regions have gaps defining a first active area in a first gap region (first MOAT) and a second active area in a second gap region (second MOAT). A drain includes drain fingers in the second MOAT interdigitated with source fingers in the first MOAT each doped second type. The DBDL is within a fingertip drift region associated drain fingertips and/or source fingertips between the first and second MOAT. A gate stack is on the semiconductor surface between source and drain. The dilution stripes have stripe widths that increase monotonically with a drift length at their respective positions.

Abstract: A power-gated electronic device and a method of operating the same is provided. The power-gated electronic device comprises a low drop out voltage power supply (LDO), an auxiliary power supply and at least one electronic domain having a power gate. The LDO provides a supply voltage to the at least one electronic domain which is coupled to a supply rail of the LDO via a switch, acting as a power gate. The auxiliary power supply comprises at least one current source which is coupled to the electronic domain via an auxiliary switch acting as an auxiliary power gate. The auxiliary power supply is configured to control the auxiliary switch as a function of a voltage difference between a reference voltage and the auxiliary supply voltage.

Abstract: A vapor cell for installation in an atomic clock or a magnetometer. The vapor cell includes a top plate, a center plate, and a bottom plate defining a cavity for passing light along an optical path. The vapor cell includes one or more condensation sites to trap condensed vapor in order to avoid blockage of the optical path.

Abstract: Embodiments of the invention provide a method to detect DSSS preambles in smart utility networks. A DSSS signal is received by a receiver and a digital sequence of samples is formed. A difference value is calculated between pairs of samples in the digital sequence of samples to form a sequence of differential values. A known preamble differential value sequence is correlated with the sequence of differential values to form a sequence of correlation values. A location of the preamble is located in the digital sequence of samples corresponding to a peak in the sequence of correlation values that exceeds a threshold value.

Abstract: Circuits and methods for providing short-circuit protection in a voltage regulator are disclosed. A voltage regulator includes a pass switch, a voltage error amplifier, a driver circuit, and a short-circuit protection circuit. The pass element is coupled to a power supply and a load, and generates an output voltage in response to a drive signal. The voltage error amplifier generates an error voltage based on a difference of a reference voltage and the output voltage and the driver circuit generates the drive signal in response to the error voltage. The short-circuit protection circuit senses the drive signal and provides a high-resistance path to the driver circuit in a short-circuit event. In a short-circuit event, the high-resistance path clamps current in the driver circuit thereby clamping a voltage difference between the first and third terminals and thereby limiting a load current in the short-circuit event.

Abstract: An integrated circuit containing an NMOS transistor with a boron-doped halo is formed by co-implanting carbon in at least three angled doses with the boron halo implants. The carbon is co-implanted at tilt angles within 5 degrees of the boron halo implant tilt angle. An implant energy of at least one of the angled carbon co-implant is greater than the implant energy of the boron halo implant. A total carbon dose of the angled carbon co-implants is at least 5 times a total boron dose of the boron halo implants. The NMOS transistor has a carbon concentration in the halo regions which is at least 5 times greater than the boron concentration in the halo regions. The co-implanted carbon extends under the gate of the NMOS transistor.

Abstract: In one embodiment, a transmitter includes a binary sequence generator unit configured to provide a sequence of reference signal bits, wherein the sequence is an inseparable function of a cell identification parameter, a cyclic prefix mode corresponding to the transmitter and one or more time indices of the sequence. The transmitter also include a mapping unit that transforms the sequence of reference signal bits into a complex reference signal, and a transmit unit configured to transmit the complex reference signal. In another embodiment, a receiver includes a receive unit configured to receive a complex reference signal and a reference signal decoder unit configured to detect a sequence of reference signal bits from the complex reference signal, wherein the sequence is an inseparable function of a cell identification parameter, a cyclic prefix mode corresponding to a transmitter and one or more time indices of the sequence.

Abstract: A method of normalizing phase measurements for a motor using a normalizing phase measurements (NPM) algorithm that a processor implements to cause a motor controller coupled to stator terminals of the phases to execute forcing a set of input current or voltage vectors (set of input vectors) including repeating the forcing after rotating the rotor through a full mechanical cycle to generate resulting current or voltage samples (resulting samples) of non-normalized phase A and phase B waveforms. The magnitude of the input vectors are sufficiently small to not move the rotor. A maximum value (x_max) and a minimum value (x_min) are determined for each of the non-normalized phase A and phase B waveforms. An offset value and normalization scale factor (NSF) are determined from the max and min values. The offsets and NSFs are applied to the non-normalized phase waveforms to generate normalized phase A and phase B waveforms.

Abstract: An image fusing method, apparatus and system for fusing images from an array of cameras, method includes selecting a camera from the array of cameras as a reference camera, estimating misalignment between the retrieved input images from the reference camera and the retrieved input images from the other cameras, estimating misalignment parameters between the reference camera and the other cameras, estimating local disparity between the reference camera image data and the other cameras based on the estimated misalignment parameters, using the estimated misalignment parameters and the estimated disparity values, mapping the image data into a reference camera grid, the retrieved input image data from the other cameras in the array of cameras is fused in the reference camera grid utilizing fractional offsets from integer coordinates, and producing an output image grid on the reference camera grid and interpolate output pixels using processed data for producing a high resolution image.

Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 5A) for an integrated circuit is disclosed. The integrated circuit includes a first ESD cell having a current path coupled between a first terminal and a second terminal. A second ESD cell has a current path coupled between the second terminal and a power supply terminal. A passive circuit is connected in parallel with one of the first and second ESD cells.

Abstract: Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.