Abstract: An electronic device comprising circuitry for providing a Power-on-Reset (POR) signal as a function of a supply voltage level of the circuitry. The circuitry comprises a Vbe-cell or a Vgs-cell comprising a first current path including a first transistor and a second current path including a second transistor. Each transistor has a control terminal for controlling a first current in the first current path and a second current in the second current path, wherein a control voltage level is commonly applied to the control terminals of the first and the second transistor. The control voltage level is derived from the current supply voltage level of the circuitry, and the circuitry further comprises a POR output node for providing a POR output signal, which changes from a first state to a second state in response to the ratio of the magnitudes of the first current and the second current.

Abstract: An apparatus, system and method for asynchronously reducing power in a power domain. In one embodiment, the method includes: (1) receiving a sleep command for the power domain, (2) receiving, upon receiving the sleep command, an affirmative retention status signal denoting that a retention area in the power domain has stored data, (3) receiving, upon receiving the sleep command, an affirmative isolation status signal that denotes that an isolation of the power domain has occurred and (4) providing a power domain off command to the power domain upon receiving at least the sleep command, the affirmative status retention signal and the affirmative status isolation signal. In another embodiment, multiple enable signals are employed to generate a “glitch-free” control for a power switch.

Abstract: Disclosed herein is a method of manufacturing a semiconductor package with a solder standoff on lead pads that reach to the edge of the package (non-pullback leads). It includes encapsulating a plurality of die on a lead frame strip. The lead frame strip comprises a plurality of package sites, which further comprises a plurality of lead pads and a die pad. The method also includes forming a channel between the lead pads of nearby package sites without singulating the packages. Another step in the method includes disposing solder on the lead pads, the die pad, or the lead pads and the die pads without substantially covering the channel with solder. The manufacturing method further includes singulating the packages.

Abstract: A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).

Abstract: An apparatus and method for spatially and temporally dithering pixels. A pixel comprising at least one color component of a first size is provided. A dither addend is determined based on the display position of the pixel. The dither addend is added to the color component, and the color component is rounded to a second size. In one embodiment, a first frame may be provided for displaying the first pixel, the dither addend corresponding to the first frame. One or more additional frames for displaying the first pixel are provided, and one or more additional dither addends corresponding to the first pixel in the additional frames may be determined. The dither addend is different from the additional dither addends, and the additional dither addends are different from each other.

Abstract: A post-mold plated semiconductor device has an aluminum leadframe (105) with a structure including a chip mount pad and a plurality of lead segments without cantilevered lead portions. A semiconductor chip (210) is attached to the chip mount pad, and conductive connections (212) span from the chip to the aluminum of the lead segments. Polymeric encapsulation material (220), such as a molding compound, covers the chip, the connections, and portions of the aluminum lead segments without leaving cantilevered segment portions. Preferably by electroless plating, a zinc layer (301) and a nickel layer (302) are on those portions of the lead segments, which are not covered by the encapsulation material including the aluminum segment surfaces (at 203b) formed by the device singulation step, and a layer (303) of noble metal, preferably palladium, is on the nickel layer.

Abstract: An program counter address comparator includes two comparators comparing an input program counter address with respective reference addresses. The comparators produce a match indication on selectable criteria, such as greater than, less than, equal to, not equal to, less than or equal to, and greater than or equal to, and can be selectively chained. Input multiplexers permit selection of either the program counter address bus or a secondary address bus. The reference addresses and control functions are enabled via central processing unit accessible memory mapped registers.

Abstract: System and method for a multi-carrier ultra-wideband (UWB) transmitter. A preferred embodiment comprises an UWB transmitter (for example, transmitter 300) taking advantage of both code division multiple access (CDMA) (for example, block 305) and orthogonal frequency division multiplexing (OFDM) (for example, block 315) techniques to create a multi-carrier UWB transmitter. The multi-carrier UWB is capable of avoiding interferers by eliminating signal transmissions in the frequency bands occupied by the interferers. An alternate embodiment using intermediate frequencies and mixers is also presented.

Abstract: A method of operating a user equipment device includes extracting at least one rank indicator (RI) from an uplink grant, and adapting a transmission rank in response to said RI. At least two transmit antennas are configured to transmit according to said transmission rank.

Abstract: A user equipment device has a control information decoder configured to receive and decode an uplink scheduling grant. A transmit module is configured to receive a rank indicator (RI) extracted by the decoder and adapt a transmission rank in response to the RI. At least two transmit antennas are configured to transmit according to the RI.

Abstract: A method of designing an analog integrated circuit (IC), a parasitic constraint analyzer and a method of determining a layout of an analog IC complies with parasitic constraints. In one embodiment, the method of designing an analog IC includes: (1) creating a schematic of an analog integrated circuit based on a set of specifications, (2) attaching parasitic constraints to the schematic, (3) creating a layout of the analog integrated circuit based on the schematic including the parasitic constraints, (4) extracting parasitic values from parasitic elements of the layout and (5) comparing the extracted parasitic values with the parasitic constraints to verify compliance therewith.

Abstract: A method of causing an interface to implement a mode from a plurality of selectable modes in which the interface operates according to a plurality of states defined by a state machine comprises sequencing through a sequence of the states, and detecting a predetermined sequence of the states. The predetermined sequence of the states represents a no-operation for at least one of the modes and also represents a mode change command.

Abstract: A semiconductor device, such as an inductor, is formed with an air gap. A first level has an intra-metal dielectric layer including one or more inductor loops, one or more vias, and one or more copper bulkhead structures. An inter-level dielectric layer is formed over the first level. An extraction via is formed through the intra-metal dielectric layer and inter-level dielectric layer. An air gap is formed between inductor loops by removing portions of the intra-metal dielectric layer coupled to the extraction via using a supercritical fluid process, and forming a non-conformal layer to seal the extraction via. The air gap may be filled with an inert gas, like argon or nitrogen.

Abstract: This invention prevents undershoot, etc., occurring in the output during the transition from intermittent control mode to continuous control mode to hinder stability, responsiveness, and low power consumption.

Abstract: Stabilization for devices such as hand-held camcorders segments a low-resolution frame into a region of reliable estimation, refines the motion vectors of that region hierarchically while at the same time updating the segmentation, finds a global motion vector for the region at high resolution, and uses the global motion vector to compensate for jitter.

Abstract: This invention provides trace address compression by comparing respective bytes of a current trace address with a stored comparison address. Only the least significant bytes of the current trace address that do not match the comparison address or are less significant than any section of the current trace address that does not match the comparison address are transmitted. This sometimes reduces the amount of data that needs to be transmitted. The comparison address is specified by a central processing unit via a memory mapped register write operation.

Abstract: This invention improves cache operation by dynamically extending one state of a clock signal supplied to a cache on operation cycles when a cache fill operation will occur. The dynamic extension of the clock signal includes delaying the clock signal, forming a waveform toggling between states upon each predetermined state transition of the delayed clock signal, selecting the clock signal when this waveform has a first stage, and selecting the delayed clock signal when this waveform has a second state. Dynamic extension is prevented during a test mode. An apparatus of this invention uses a flip-flop and a multiplexer to produce the dynamically delayed clock.

Abstract: A method and system of identifying overlays. At least some of the illustrative embodiments are methods comprising executing a traced program on a target system (the traced program comprising a plurality of overlay programs), obtaining values indicative of which of the plurality of overlays of the traced program has executed on the target system, and displaying on a display device an indication of a proportion of an execution time on the processor of the target system dedicated to each of the plurality of overlay programs.

Abstract: A Junction Field Effect Transistor (JFET) can be fabricated with a well region that include a channel region having an average dopant concentration substantially less the average doping concentration of the remaining portions of the well region. The lower average doping concentration of channel region compared to the remaining portions of the well region reduces the pinch-off voltage of the JFET.

Abstract: Various systems and methods for analog to digital conversion are disclosed. For example, some embodiments of the present invention provide analog to digital conversion systems. The analog to digital conversion systems include a first integrator and a second integrator, and a first summation element and a second summation element. An output of the first summation element is electrically coupled to the first integrator, and an output of the first integrator is electrically coupled to the second integrator. An output of the second integrator is electrically coupled to the second summation element. The analog to digital conversion systems further include an analog to digital converter that is electrically coupled to the first summation element via a digital to analog converter. An input to the analog to digital conversion system is electrically coupled to the first summation element, and the input is electrically coupled to the second summation element via a kickback filter.