Abstract: A method includes detecting removal or depletion of a power supply associated with a powered device. The powered device is configured to receive power from a power adapter via a narrow-voltage direct current/direct current (NVDC) charger and from the power supply. The method also includes, in response to the detection, disabling a dynamic power management function of the NVDC charger. The method further includes monitoring input current or input power provided to the powered device by the NVDC charger and determining if the input current or input power exceeds a threshold. In addition, the method includes, if the input current or input power exceeds the threshold, triggering a throttling of an operating clock frequency of the powered device. The method could also include (i) disabling a specified mode of operation and turning on a voltage regulator of the NVDC charger in response to the detection and (ii) providing over-voltage protection.

Abstract: An integrated circuit containing an analog MOS transistor may be formed by implanting drain extensions with exactly four sub-implants wherein at least one sub-implant implants dopants in a substrate of the integrated circuit at a source/drain gate edge of the analog MOS transistor at a twist angle having a magnitude of 5 degrees to 40 degrees with respect to the source/drain gate edge of the analog MOS transistor, for each source/drain gate edge of the analog MOS transistor, wherein a zero twist angle sub-implant is perpendicular to the source/drain gate edge. No more than two sub-implants put the dopants in the substrate at any source/drain gate edge of the analog MOS transistor. All four sub-implants are performed at a same tilt angle. No halo implants are performed on the analog MOS transistor.

Abstract: A secure demand paging system (1020) includes a processor (1030) operable for executing instructions, an internal memory (1034) for a first page in a first virtual machine context, an external memory (1024) for a second page in a second virtual machine context, and a security circuit (1038) coupled to the processor (1030) and to the internal memory (1034) for maintaining the first page secure in the internal memory (1034).

Abstract: A multi-segment capacitive successive approximation analog to digital converter (SAR ADC) is calibrated by determining an error voltage for each of a plurality of most significant bit (MSB) capacitors in a first segment using a calibration DAC. The first segment is connected to the second segment by an attenuation capacitor. Each of the error voltages corresponding to the MSB capacitors is digitized to form a set of digitized error voltages. An error voltage for each of a plurality of less significant bit (LSB) capacitors in at least the second segment is calculated by summing the set of digitized error voltages to form a sum of error voltages (sum(e)) and assigning a percentage of sum(e) as the error voltage for each of the LSB capacitors, such that a mismatch in the attenuation capacitor is mitigated.

Abstract: The present invention is drawn to a device for use with first stereoscopic data, second stereoscopic data and a display device. The device includes an input portion, a convergence data detecting portion, a convergence plane portion, a comparing portion and a modification portion. The input portion can receive the first stereoscopic data and the second stereoscopic data. The convergence data detecting portion can detect first convergence data within the first stereoscopic data and can detect second convergence data within the second stereoscopic data. The convergence plane portion can determine a first convergence plane based on the first convergence data and can determine a second convergence plane based on the second convergence data. The comparing portion can compare the first, convergence plane and the second convergence plane and can generate a convergence plane comparison. The modification portion can modify the first convergence data based on the convergence plane comparison.

Abstract: A method to detect a gas absorption line that includes alternately transmitting and sweeping two radio frequency (RF) signals through an absorption cell, wherein the two RF signals are transmitted at different frequencies separated by a range and are swept across a span of frequencies in a microwave and millimeter wave regions of a frequency spectrum. Receiving the RF signals by a receiver and analyzing the received signals by a closed loop system for relative absorption by a gas due to an absorption line of the gas in the span of the swept frequencies. Detecting the absorption line of the gas when the two RF signals straddle the gas absorption line and the relative absorption by the two RF signals is equal.

Abstract: Power factor correction (PFC) apparatus, controllers, and methods for operating bridgeless totem pole power factor correction converters in which AC input voltage polarity is detected for designation of active and freewheeling switches of the totem pole circuit, a nominal freewheeling switch on-time is determined according to a Volt×Second balance relationship, and the voltage across the designated active switch is sensed and used to selectively modify or offset the nominal freewheeling switch on-time to provide a computed freewheeling switch on-time for the next switching cycle to facilitate zero voltage switching of the active switch.

Abstract: An apparatus is provided. In the apparatus, a demultiplexer is configured to receive an input signal, and each of a plurality of sample buffers are coupled to the demultiplexer. A first multiplexer is coupled to each of the sample buffers. A filter is coupled to the first multiplexer. A bypass delay circuit is coupled to the first multiplexer, and a second multiplexer is coupled to the filter and the bypass delay circuit.

Abstract: A method of determining angular position (A) of a rotor of an N-phase permanent magnet motor (PMM). A processor having an associated stored angular position determination (APD) algorithm is programmed to implement the algorithm to cause an associated motor controller to execute steps including forcing one vector at a time a phase vector set of current or voltage vectors to stator terminals of windings for the N-phases a positive and negative magnitude vector, wherein the vector magnitude is sufficiently small to not move the rotor, and a time duration for the forcing current or voltage vectors is essentially constant. The resulting stator current or voltage levels are measured for each current or voltage vector. An N-dimension current vector or voltage vector is generated from superposition of the resulting stator current levels or resulting stator voltage levels. The N-dimension current vector or voltage vector is used to determine angular position.

Abstract: A semiconductor device with a buried layer has a deep trench structure abutting the buried layer and a self-aligned sinker along sidewalls of the deep trench structure. The semiconductor device may be formed by forming a portion of a deep trench down to the buried layer, and implanting dopants into a substrate of the semiconductor device along sidewalls of the deep trench, and subsequently forming a remainder of the deep trench extending below the buried layer. Alternatively, the semiconductor device may be formed by forming the deep trench to extend below the buried layer, and subsequently implanting dopants into the substrate of the semiconductor device along sidewalls of the deep trench.

Abstract: A system can include a processing core to execute machine readable instructions. The system can also include a memory accessible by the processor core. The memory can include preprogrammed test data that characterizes one of an impedance of a processor and a current output to the processor during execution of a test routine. The processor can include the processing core and the one of the impedance of the processor and the current output to the processor is based on a power measurement taken during execution of a test routine. The power measurement can be taken with a current sensor that is at least one of lossy or at least about 98% accurate.

Abstract: A system includes first and second processing components, a qualified based splitter component, a first and second configurable cache element and an arbiter component. The first data processing component generates a first request for a first portion of data at a first location within a memory. The second data processing component generates a second request for a second portion of data at a second location within the memory. The qualifier based splitter component routes the first request and the second request based on a qualifier. The first configurable cache element enables or disables prefetching data within a first region of the memory. The second configurable cache element enables or disables prefetching data within a second region of the memory. The arbiter component routes the first request and the second request to the memory.

Abstract: An integrated circuit contains a flash cell in which the top gate of the sense transistor is a metal sense gate over the floating gate. The source/drain regions of the sense transistor extend under the floating gate so that the source region is separated from the drain region by a sense channel length less than 200 nanometers. The floating gate is at least 400 nanometers wide, so the source/drain regions of the sense transistor extend under the floating gate at least 100 nanometers on each side. The integrated circuit is formed by forming the sense transistor source and drain regions before forming the floating gate.

Abstract: A set of radar data is organized as a two dimensional (2D) array with multiple lines of data. A 2D cross point analysis is performed on each set of data to detect objects in range of the radar system. A set of candidate objects is identified by performing an initial one dimensional (1D) analysis on a line of data along a first axis of the set if data to determine a candidate location of each candidate object along the first axis; however, the set of candidate objects may include false objects. The set of candidate objects is pruned by performing a cross 1D analysis of the data along a second axis of the set of data at a position corresponding to each candidate location along the first axis to select a set of most likely candidate objects from the set of candidate objects.

Abstract: A video output supervisor includes a test region indicator for verifying that the commanded output to specific areas of a display is valid. Areas reserved displaying safety-critical data in the data frame to be displayed can be supervised for the presence and status of display indicators of the safety-critical data. The confidence of the supervision can be increased by measuring other display and frame parameters in conjunction with supervising the indicators of the safety-critical data.

Abstract: A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol. The active protocol is used by the communications interface to exchange information while the remaining protocols of the plurality of protocols remain inactive. The state machine sequences through a series of states that cause the communications interface to operate according to the active protocol, and that are designated as inert sequences under the remaining protocols.

Abstract: An electrostatic discharge (ESD) protection integrated circuit (IC) includes a substrate having a semiconductor surface, a high power supply rail (VDD) and a low power supply rail (VSS) on the semiconductor surface. A trigger circuit including at least one trigger input and at least one trigger output is coupled between VDD and VSS. An active shunt including at least a large MOSFET is coupled between VDD and VSS. The trigger output is coupled to a gate electrode of the large MOSFET, and at least one diode or diode connected transistor (blocking diode) is coupled between VDD and the trigger circuit, within the trigger circuit or between the trigger output and gate electrode.

Abstract: The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or DMA, and the EMIF (External Memory InterFace) in a multicore SoC. The invention unifies all transaction sizes belonging to a slave previous to arbitrating the transactions in order to reduce the complexity of the arbitration process and to provide optimum bandwidth management among all masters. Two consecutive slots are assigned per cache line access to automatically guarantee the atomicity of all transactions within a single cache line. The need for synchronization among all the banks of a particular SRAM is eliminated, as synchronization is accomplished by assigning back to back slots.

Abstract: A frequency detection technique includes generating first and second signals such that a frequency of the first signal is the same as a frequency of the second signal and such that the second signal is phase-shifted by a fixed amount with respect to the first signal. The technique further includes generating a third signal having a frequency that corresponds to an absolute value of a difference between the frequency of the first signal and an integer multiple of a frequency of the reference signal. The technique further includes generating a fourth signal having a frequency that corresponds to an absolute value of a difference between the frequency of the second signal and an integer multiple of the frequency of the reference signal. The technique further includes generating an fifth signal indicative of whether a phase relationship between the third and fourth signals is a leading phase relationship, a lagging phase relationship, or an in-phase relationship.

Abstract: A tunable quadrature oscillator includes a first oscillator having an output, a second oscillator having an output, and a variable gain amplifier. The variable gain amplifier includes an input coupled to the output of the second oscillator, and an output inductively coupled to the output of the first oscillator.