Abstract: A process (111,101) of sending packets of real-time information at a sender (311) includes initially generating packets of real-time information with a source rate (s11) greater than zero kilobits per second, and a time or path or combined time/path diversity rate (d11) initially being at least zero kilobits per second. Sending the packets results in a quality of service QoS, optionally measured at the sender (311). Rate/diversity adaptation decision may be performed at receiver (361?) instead. When the QoS is on an unacceptable side of a threshold of acceptability (Th1), the sender increases the diversity rate (d11 to d22) and sends not only additional ones of the packets of real-time information but also sends diversity packets at the increased diversity rate (d22). Increasing the diversity rate (d11 to d22) while either reducing or maintaining the overall transmission rate (sij+dij) is an important new improvement.

Abstract: An all digital PLL system generates an analog oscillator signal at intermediate frequencies to achieve averaged oscillator frequencies at an extremely high frequency resolution. The PLL system includes a digitally controlled oscillator (10) with a digital control input and an analog signal output, and a feedback loop with a digital loop filter (16) for generating a digital control signal for the digitally controlled oscillator (10). The digital loop filter (16) has a first output providing an integer part (nint) of the digital control signal and a second output providing a fractional part (n??) of the digital control signal.

Abstract: Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is accessible external to the IC, it is generally preferred to have selectivity on which Tap domain or Tap domains are accessed. Therefore Tap domain selection circuitry may be included in ICs and placed in the scan path along with the Tap domains. Ideally, the Tap domain selection circuitry should only be present in the scan path when it is necessary to modify which Tap domains are selected in the scan path. The present disclosure describes a novel method and apparatus which allows the Tap domain selection circuitry to be removed from the scan path after it has been used to select Tap domains and to be replaced back into the scan path when it is necessary to select different Tap domains.

Abstract: A multi-threaded processor adapted to couple to external memory comprises a controller and data storage operated by the controller. The data storage comprises a first portion and a second portion, and wherein only one of the first or second portions is active at a time, the non-active portion being unusable. When the active portion does not have sufficient capacity for additional data to be stored therein, the other portion becomes the active portion. Upon a thread switch from a first thread to a second thread, only one of the first or second portions is cleaned to the external memory if one of the first or second portions does not contain valid data.

Abstract: A method for merging branch information with sync points is disclosed herein. The method comprises determining whether a sync point is to be generated concurrent with a branch instruction and generating said sync point to include a program counter value and to indicate that the sync point occurred concurrent with the branch instruction.

Abstract: One embodiment of the present invention includes a data transmission system. The system comprises a data transmitter that provides a plurality of data bits over at least one data line. The data transmitter comprises a clock that provides a clock signal associated with timing for latching the plurality of data bits and a data encoder configured to encode error data associated with the data transmission system in the clock signal.

Abstract: Layered code-excited linear prediction (CELP) speech encoders have progressively weaker perceptual weighting filters for each of the successive enhancement layers and decoders have progressively weaker short-term postfilters for increased bit rates (increased number of enhancement layers decoded) and a long-term postfilter for all bit rates.

Abstract: An instrumentation amplifier includes first (11A) and second (12A) input amplifiers having outputs (15A,B) coupled to an output amplifier (13). A first auto-zero stage (20) in the first input amplifier is auto-zeroed to a first voltage level (VREFL), a first input signal (Vin+) is amplified by a second auto-zero stage (24) in the first input amplifier, and the amplified first input signal is coupled to the output amplifier, during a first phase (A). A third auto-zero stage (44) in the second input amplifier is auto-zeroed to a second voltage level (VREFH), a second input signal (Vin?) is amplified by a fourth auto-zero stage (40) in the second input amplifier, and the amplified second input signal is coupled to the output amplifier, during a second phase (B). The second auto-zero stage is auto-zeroed to the first voltage level, the first input signal is amplified by the first auto-zero stage (20), and the amplified first input signal is coupled to the output amplifier, during a third phase (C).

Abstract: A semiconductor device comprising source and drain regions and insulating region and a plate structure. The source and drain regions are on or in a semiconductor substrate. The insulating region is on or in the semiconductor substrate and located between the source and drain regions. The insulating region has a thin layer and a thick layer. The thick layer includes a plurality of insulating stripes that are separated from each other and that extend across a length between the source and the drain regions. The plate structure is located between the source and the drain regions, wherein the plate structure is located on the thin layer and portions of the thick layer, the plate structure having one or more conductive bands that are directly over individual ones of the plurality of insulating stripes.

Abstract: An integrated circuit (200) includes one of more transistors (210) on or in a substrate (10) having semiconductor surface layer, the surface layer having a top surface. At least one of the transistors are drain extended metal-oxide-semiconductor (DEMOS) transistor (210). The DEMOS transistor includes a drift region (14) in the surface layer having a first dopant type, a field dielectric (23) in or on a portion of said surface layer, and a body region of a second dopant type (16) within the drift region (14). The body region (16) has a body wall extending from the top surface of the surface layer downwards along at least a portion of a dielectric wall of an adjacent field dielectric region. A gate dielectric (21) is on at least a portion of the body wall. An electrically conductive gate electrode (22) is on the gate dielectric (21) on the body wall.

Abstract: The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.

Abstract: In one embodiment, a transmitter includes a binary sequence generator unit configured to provide a sequence of reference signal bits, wherein the sequence is an inseparable function of a cell identification parameter, a cyclic prefix mode corresponding to the transmitter and one or more time indices of the sequence. The transmitter also include a mapping unit that transforms the sequence of reference signal bits into a complex reference signal, and a transmit unit configured to transmit the complex reference signal. In another embodiment, a receiver includes a receive unit configured to receive a complex reference signal and a reference signal decoder unit configured to detect a sequence of reference signal bits from the complex reference signal, wherein the sequence is an inseparable function of a cell identification parameter, a cyclic prefix mode corresponding to a transmitter and one or more time indices of the sequence.

Abstract: The present invention provides, in one embodiment, a method of manufacturing a metal oxide semiconductor (MOS) transistor (100). The method comprises forming an active area (105) in a substrate (115), wherein the active area (105) is bounded by an isolation structure (120). The method further includes placing at least one stress adjuster (130) adjacent the active area (105), wherein the stress adjuster (130) is positioned to modify a mobility of a majority carrier within a channel region (155) of the MOS transistor (100). Other embodiments of the present invention include a MOS transistor device (200) and a process (300 ) for constructing an integrated circuit.

Abstract: Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal, which is a ‘mid gap’ metal, is manipulated in first and second regions by second and third metals, respectively, to move the work function of the first metal in opposite directions in the different regions. The resulting work functions in the different regions correspond to that of different types of the transistors that are to be formed.

Abstract: Device comprising an ohmic via contact, and method of fabricating thereof. A preferred embodiment comprises forming a metal layer over a substrate, forming a conductive barrier layer over the metal layer, depositing an insulating layer over the conductive barrier layer, creating an opening in the insulating layer to expose the conductive barrier layer, and forming a via contact in the opening. The conductive barrier layer protects the metal layer by preventing the formation of an oxide layer, which could reduce conductivity.

Abstract: The invention provides a method of fabricating a semiconductive device [200]. In this embodiment, the method comprises depositing a hydrocarbon layer [294] over a semiconductive substrate, forming an interconnect structure [295, 297] within the hydrocarbon layer [294], and removing the hydrocarbon layer [294] by sublimation.

Abstract: A semiconductor device with a semiconductor die thereon and a contactor board are electrically coupled when the electrically conductive elements on the semiconductor device and the contactor board are in physical contact. A continuous electrically conductive path is formed with electrically conductive elements involving both the semiconductor device and the contactor board. A complete electrical circuit involving both the semiconductor device and the contactor board is formed only when the relative orientation of the semiconductor device and the contactor board have predetermined relationship and the electrically conductive elements of the two boards are in good physical contact.

Abstract: A data transfer apparatus with hub and ports includes design configurable hub interface units (HIU) between the ports and corresponding external application units. The configurable HIU provides a single generic superset HIU that can be configured for specific more specialized applications during implementation as part of design synthesis. Configuration allows the super-set configurable HIU to be crafted into any one of several possible special purpose HIUs. This configuration is performed during the design phase and is not applied in field applications. Optimization aimed at eliminating functional blocks not needed in a specific design and simplifying and modifying other functional blocks allows for the efficient configuring of these other types of HIUs. Configuration of HIUs for specific needs can result in significant savings in silicon area and in power consumption.

Abstract: A wireless communications device (110) has a digital section (800) and a radio frequency section (840). The digital section (800) does setup and execution on a set of data in at least first and second threads concurrently in a series of overlapping iterations by dividing the set of data into at least two different subsets and concurrently reading and writing in both subsets. A state machine (1010, 1100) is shared by the setup and execution iterations. Two or more memory units (930, 940) segregate the set of data, the predetermined size of the set of data in the memories (930, 940) combined comprehending the total number of addresses occupied by the set of data utilized in operation of circuitry (910). Dirty bits (1430) are accessible at addresses corresponding to addresses in the memory. A selector circuit (1412) has a selector output selectively coupled to an address line, and to a data line.

Abstract: An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is adapted to collect the information from caches having a common cache level. The software also causes the processor to prioritize the caches having the common cache level such that the caches are displayable as having different cache levels.