Abstract: A configurable voltage regulator (28; 128) operable in either of two selectable modes or topologies is disclosed. In one disclosed embodiment, the voltage regulator (28) can operate as a linear regulator or a switching regulator. A gate driver (35) and an error amplifier (36) is used in each mode. Configuration switches (34) are controlled by a configuration amplifier (40) to connect the error amplifier (36) to the gate driver (35) in the linear regulator mode, or to connect the error amplifier (36) to circuitry (42, 44, 46) for controlling the gate driver (35) in switching regulator mode. In another disclosed embodiment, the voltage regulator (128) generates a negative polarity regulated voltage according to a switching regulator or charge pump topology.
Abstract: A method for improving high-? gate dielectric film (104) properties. The high-? film (104) is subjected to a two step anneal sequence. The first anneal is performed in a reducing ambient (106) with low partial pressure of oxidizer to promote film relaxation and increase by-product diffusion and desorption. The second anneal is performed in an oxidizing ambient (108) with a low partial pressure of reducer to remove defects and impurities.
Type:
Grant
Filed:
October 25, 2007
Date of Patent:
October 13, 2009
Assignee:
Texas Instruments Incorporated
Inventors:
Luigi Colombo, James J. Chambers, Mark R. Visokay, Antonio Luis Pacheco Rotondaro
Abstract: A method of processing semiconductor wafers comprises forming a pattern of recesses in an exposed surface of each wafer in a lot, prior to an epitaxy step. At least one recessed test structure is included in the pattern of recesses. At least one dimension of the recessed test structure is determined prior to the epitaxy step, then a corresponding dimension of an epitaxial structure grown above the recessed test structure in the epitaxy step is measured. A deviation between the dimension of the recessed test structure and the dimension of the epitaxial structure is determined and, from the deviation, the process temperature at which the epitaxy step was performed is determined. In case the deviation exceeds a predetermined limit, the temperature in the process chamber is adjusted for a subsequent lot of wafers to be processed.
Abstract: A profiling system. At least some of the illustrative embodiments are integrated circuit devices comprising a processing circuit configured to execute a target program (the processing circuit having a plurality of registers), a trace system operatively coupled to the processing circuit (the trace system configured to collect trace data comprising the values of the plurality of registers, and the trace system configured to send the trace data for use by a debug program), a first memory operatively coupled to the processing circuit (the first memory comprising instructions to be executed by the processing circuit), and a memory location operatively coupled to the trace system (the memory location writable by the target program). The trace system is configured to send a value stored in the memory location to the host computer only when the value is newly written.
Abstract: A method and a material for creating an antireflective coating on an integrated circuit. A preferred embodiment comprises applying a dark polymer material on a reflective surface, curing the dark polymer material, and roughening a top surface of the dark polymer material. The roughening can be achieved by ashing the dark polymer material in an ash chamber. The dark polymer material, preferably a black matrix resin or a polyimide black matrix resin, when ashed in an oxygen rich atmosphere for a short period of time, forms a surface that is capable of absorbing light as well as randomly refracting light it does not absorb. A protective cap layer may be formed on top of the ashed dark polymer material to provide protection for the dark polymer material.
Abstract: The present invention facilitates semiconductor device operation and fabrication by providing a cap-annealing process that improves channel electron mobility without substantially degrading PMOS transistor devices. The process uses an oxide/nitride composite cap to alter the active dopant profile across the channel regions. During an annealing process, dopants migrate out of the Si/SiO2 in a channel region thereby altering the dopant profile of the channel region. This altered profile generally improves channel mobility thereby improving transistor performance and permitting smaller density designs.
Abstract: A transistor comprises a source region of a first conductivity type and electrically communicating with a first semiconductor region. The transistor also comprises a drain region of the first conductivity type and electrically communicating with a second semiconductor region that differs from the first semiconductor region. An interface exists between the first semiconductor region and the second semiconductor region. The transistor also comprises a voltage tap region comprising at least a portion located in a position that is closer to the interface than the drain region. A mixed technology circuit is also described.
Abstract: The present invention provides, in one aspect, the present invention provides, in one embodiment, a method of conditioning a deposition chamber 100. This method comprises placing an undercoat on the walls of a deposition chamber 100 and depositing a pre-deposition coat over the undercoat with a plasma gas mixture conducted at a high pressure and with high gas flow.
Abstract: Video signals in a video stream are encoded by inserting reference signals in the video stream such that the encoded video stream carry both reference signals and video signals being coded. In the decoding stage, reference images generated from the reference signals are detected and used for identifying the encoded video signals based upon the profiles of the detected reference images. An imaging architecture capable of using the coding scheme comprises a shutter that can be implemented as a dual-processor configuration.
Type:
Application
Filed:
April 4, 2008
Publication date:
October 8, 2009
Applicant:
Texas Instruments Incorporated
Inventors:
Stephen W. Marshall, Michael David Mc Cormick, Henry William Neal, Stanford Porter Hudson
Abstract: For combining light from different light sources that are spatially apart, an optical system comprises a prism assembly that comprises a totally-internally-surface and a dichroic filter. The totally-internally-surface and the dichroic filter are configured for reflecting light of different colors or polarizations, so as to combine light of different polarization or colors into a single beam.
Abstract: For combining light from different light sources in a light source, dichroic filters are displaced individually according to the physical arrangement of the light sources such that the reflected light from the dichroic filters is coincident in angle and space.
Abstract: Embodiments of the present disclosure provide a routing engine, a method of routing a test probe and a testing system employing the router or the method. In one embodiment, the routing engine is for use with a test unit having at least one test probe and includes an analysis unit configured to analyze alternative test probe routing sequences that employ representative circuit chips of a semiconductor wafer to be tested by the test unit. The routing engine also includes a selection unit configured to select at least one of the test probe routing sequences as a test probe path for testing the semiconductor wafer based on a total cost of travel for the test probe path.
Type:
Grant
Filed:
November 7, 2007
Date of Patent:
October 6, 2009
Assignee:
Texas Instruments Incorporated
Inventors:
Rex W. Pirkle, Sean M. Malolepszy, Michael W. Perry, George Reeves
Abstract: The present invention provides, in one embodiment, a method (100) of manufacturing a semiconductor device. A conventionally formed reticle is positioned over a resist located on a substrate (110). A radiation path through the reticle and a window assembly located between a radiation source and resist (120), is considered. It is determined whether or not the radiation would expose a predefined blocking area of the resist within the exposure zone (130). If the radiation would expose a blocking area, then the window assembly is configured to prevent radiation from exposing the blocking area in the exposure zone (140). Other embodiments include a window assembly (300) and system (400) to facilitate manufacturing of the semiconductor device according to the method (100).
Type:
Grant
Filed:
June 11, 2003
Date of Patent:
October 6, 2009
Assignee:
Texas Instruments Incorporated
Inventors:
Basab Chatterjee, Richard L. Guldi, Keith W. Melcher
Abstract: Precision integrated time reference circuits are disclosed. Preferred embodiments provide time reference circuits that are relatively insensitive to variations in process, supply, and temperature. A preferred embodiment of the invention is disclosed in which a relaxation oscillator according to the invention includes a reference voltage circuit configured to maintain a reference voltage in proportion to actual circuit resistance values. Aspects of the invention also include dynamic compensation for variations in temperature.
Type:
Grant
Filed:
April 7, 2005
Date of Patent:
October 6, 2009
Assignee:
Texas Instruments Incorporated
Inventors:
Narasimhan Trichy Rajagopal, Patrick Peter Siniscalchi
Abstract: System and method for preventing resin-based adhesive from contacting a substrate to minimize resin bleed-out and contamination. A preferred embodiment comprises a semiconductor device having a die mounted on a substrate, first and second gold surfaces formed on the substrate, a trench formed between the first and second gold surfaces, resin-based adhesive applied to the first gold surface, and a heat sink bonded to the resin-based adhesive.
Type:
Grant
Filed:
March 12, 2007
Date of Patent:
October 6, 2009
Assignee:
Texas Instruments Incorporated
Inventors:
Sergio V. Martinez, Boon Hor Lee, Karen Lynne Robinson
Abstract: A signal driver having a selectable aggregate slew rate, a method of driving a signal driver and a signal driver incorporating the driver or the method. The driver includes plural partial drivers configured to output signals based on time constants established by corresponding plural time-delay networks associated therewith. The signal driver further includes a slew rate selector coupled to the plural time-delay networks and configured to provide a common signal thereto to cause the plural time-delay networks to achieve target time constants, the target time constants causing the output signals to be generated such that the signal driver achieves the selectable aggregate slew rate.
Abstract: We disclose the structure of a JFET device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It has a buried layer that is electrically communicable to a drain terminal. It has a channel region over the buried layer contacting gate regions that connect to a gate terminal. The channel region, of which the length spans the distance between the buried layer and a source region, is connected to a source terminal. The device current flows in the channel substantially perpendicularly to the top surface of the substrate.
Type:
Grant
Filed:
December 12, 2006
Date of Patent:
October 6, 2009
Assignee:
Texas Instruments Incorporated
Inventors:
Sameer P Pendharker, Pinghai Hao, Xiaoju Wu
Abstract: System and method for synchronizing the low speed mirror movement of a mirror display system with incoming frame or video signals, and synchronizing buffered lines of video data to the independently oscillating scanning mirror. According to one embodiment of the invention, the peak portions of the low speed cyclic drive signal are synchronized with the incoming frames of video by compressing or expanding the peak portion or turn around portion so that each video frame begins at the same location on the display screen. The actual position of the high frequency mirror is determined by sensors and a “trigger” signal is generated to distribute the signals for each scan line such that the scan lines are properly positioned on the display.
Type:
Grant
Filed:
January 20, 2006
Date of Patent:
October 6, 2009
Assignee:
Texas Instruments Incorporated
Inventors:
Eric Gregory Oettinger, James Eugene Noxon
Abstract: In accordance with the present invention, a system and method to increase die stand-off height in a flip chip are provided. The system includes a plurality of separator pedestals disposed between a first face of a die and a second face of a substrate, the substrate positioned generally parallel with, and spaced apart from, the die, and the first face being opposite the second face. The plurality of separator pedestals are operable to selectively force the die and substrate apart, increasing the stand-off height of the flip chip assembly.
Abstract: A method is provided to decode data encoded by any block code in a manner that substantially improves the error correction capability of the block codes, and that is independent of the encoder. The structure associated with the method desirably allows the testing of those hypotheses that are known to exist, such that one can use the a priori knowledge of the possible set of hypotheses to only search from among them. The method of decoding data is both advantageous and desirable since knowing the subset of the code word space that is being utilized in essence allows the distance between the code words to be increased yielding significant decoding benefits.