Abstract: A system has a leadframe with leads and a pad. The pad surface having a portion recessed with a depth and an outline suitable for attaching a semiconductor chip. A first chip is vertically stacked to the opposite pad surface. A clip is vertically stacked on the first chip and tied to a lead. A second chip has a terminal attached to the recessed portion and terminals co-planar with the un-recessed portion. A second chip is attached to the clip.

Abstract: A method for a DC to DC converter with a pseudo constant switching frequency is disclosed herein. For example, some embodiments provide a DC to DC converter having a switch connected to a switching node to control a voltage of the switching node, and a switching controller that is adapted to turn on and off the switch at a substantially constant frequency based at least in part on the voltage of the switching node. The switching controller includes a modulator connected to a control electrode of the switch and that is adapted to actuate and deactuate the switch, and a first timer that is connected to the switching node and to the modulator. The first timer uses the voltage of the switching node to determine an on-time for the switch.

Abstract: A flip-flop is disclosed that utilizes low area. The flip-flop includes a tri-state inverter that receive a flip-flop input, a clock input and an inverted clock input. A master latch receives an output of the tri-state inverter. The master latch includes a common inverter. A slave latch is coupled to the master latch. The common inverter is shared between the master latch and the slave latch. An output inverter is coupled to the common inverter and generates a flip-flop output.

Abstract: The disclosure provides an analog to digital converter (ADC). The ADC includes a comparator that receives a threshold voltage. A set of elementary capacitors is coupled to the comparator, and receives one of an input voltage and a set of reference voltages. A set of M offset capacitors is coupled to the comparator, and receives one of a primary voltage and a secondary voltage, M is an integer. A difference in the primary voltage and the secondary voltage varies linearly with temperature.

Abstract: Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data input signal and a data output signal of the scan topology. An input data value and an output data value for each of the plurality of components is sampled and recorded. A low logic value is then scanned through the scan path and recorded at each component. The scan topology may be determined based on the recorded data values and the recorded scan values.

Abstract: Channel state information (CSI) feedback in a wireless communication system is disclosed. A precoding matrix is generated for multi-antenna transmission based on precoding matrix indicator (PMI) feedback, wherein the PMI indicates a choice of precoding matrix derived from a matrix multiplication of two matrices from a first codebook and a second codebook. In one embodiment, the first codebook comprises at least a first precoding matrix constructed with a first group of adjacent Discrete-Fourier-Transform (DFT) vectors. In another embodiment, the first codebook comprises at least a second precoding matrix constructed with a second group of uniformly distributed non-adjacent DFT vectors.

Abstract: Traditionally, designs have been very conservative on power grid design using higher margins than those needed for safe operation. This is especially true for process driver designs which may not have enough data on process characteristics. This invention allows us to recoup these inefficiencies and to speed up the power up/power down dynamically. This invention sequences plural power supply switches serially or in plural parallel sets as set by a wake up mode.

Abstract: Embodiments of the invention provide systems and methods for a cipher then segment approach in a Power Line Communication (PLC). A node or device generates frames to be transmitted to a destination node in the PLC network. A processor in the node is configured to generate a data payload comprising data to be sent to the destination node. The processor divides the data payload into two or more payload segments and encrypts the payload segments. The processor creates a frame for each of the encrypted payload segments, wherein each frame comprises a message integrity code. The processor creates a segment identifier for each frame using the message integrity code and an authentication key that is shared with the destination PLC node. The segment identifier is added to each frame.

Abstract: Described examples include controllers and methods for controlling an inverter to drive a load and for detecting load faults by determining phasor values representing voltages and currents associated with the individual load phases based on sets of input values, determining voltage and current sequence components according to the phasor values, determining a sequence impedance value by recursively solving a set of update equations at least partially according to the voltage and current sequence components, and detecting a load fault when the sequence impedance value exceeds a threshold value.

Abstract: The circuitry of an optical receiver reduces the ambient DC component and the pleth DC component to leave a pleth signal with substantially only a pleth AC component. The circuitry also provides gain control and can provide transmit power control to change the range of the pleth AC component to occupy a desired input range of an analog-to-digital converter.

Abstract: A clock dithering circuit that provides cancellation of digital noise spurs is disclosed. The clock dithering circuit includes a control unit that receives an input clock. An ICG (integrated clock gating) cell receives the input clock and receives an enable signal from the control unit. The ICG cell generates a gated clock. A coarse dither unit receives the gated clock and receives a coarse select signal from the control unit. The coarse dither unit generates a coarse dither clock. A fine dither unit receives the coarse dither clock and receives a fine select signal from the control unit. The fine dither unit generates a fine dither clock.

Abstract: A radiation sensor (27) includes a radiation sensor chip (1) including first (7) and second (8) thermopile junctions connected to form a thermopile (7,8). The first thermopile junction is disposed in a floating portion of a dielectric membrane (3) thermally insulated from a silicon substrate (2) of the chip, and the second thermopile junction is disposed in the dielectric membrane directly adjacent to the substrate. Bump conductors (28) are bonded to corresponding bonding pads (28A) coupled to the thermopile (7,8) to physically and electrically connect the chip to conductors on a printed circuit board (23). The silicon substrate transmits infrared radiation to the thermopile while blocking visible light.

Abstract: A clock data recovery system is described. It includes a high pass filter for transmitting a filtered data signal in response to receiving an input data signal; an adder for summing the filtered data signal with a feedback signal, wherein the adder produces a summed input signal; a plurality of clocked data comparators for receiving the summed input signal, wherein the clocked data comparators determine an input data bit value; a plurality of clocked error comparators for receiving an error signal associated with clock recovery and DFE tap adaption; an equalization and adaptation logic for selecting an error sample such that a phase associated with the error sample is locked at h0=h1+h2; and a phase mixer for transmitting a delay in response to receiving the phase and the delay is transmitted to the clocked-data comparators and the clocked-error comparators.

Abstract: A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.

Abstract: A multiple phase dc to dc converter with a shared bootstrap capacitor. In an embodiment, a multiple phase buck converter is disclosed including a plurality of n switching stages, each coupled to a corresponding switching node, each further including a high side driver MOS device coupled between a terminal for a positive voltage supply terminal and the corresponding switching node; and an inductor coupled in parallel between the corresponding switching node and an output terminal configured for providing the DC output voltage; and high side driver control circuitry configured to selectively couple a shared bootstrap capacitor to a gate terminal of each of the high side drivers, wherein the shared bootstrap capacitor is configured to charge a gate capacitance of each of the high side driver MOS devices. Additional embodiments are disclosed.

Abstract: The present disclosure provides methods and apparatus for adapting a relatively high data rate second order SERDES receiver to receive relatively low data rate serial data, the receiver having a jog realignment by and having means for receiving the serial data as a plurality of repeated bits at the high data rate; framing the data as frames of repeated bits of the same value; examining the bits of the frame for the presence of bits which are not of the same value; upon detecting such a presence that is indicative of a framing error jogging the SERDES receiver for frame realignment; and supplying to an output of the SERDES receiver one of the bits of said same value from each frame at the low data rate.

Abstract: An input/output (IO) circuit includes a first bias circuit and a second bias circuit coupled to a node. A first capacitor and a second capacitor are being cascaded and coupled to the node. The node is defined between the first capacitor and the second capacitor. A pad is coupled to the node. The first bias circuit maintains a voltage at the node below a threshold during a transmit mode and a receive mode of the IO circuit and the second bias circuit maintains the voltage at the node below the threshold during the receive mode. The voltage at the node is dependent on a voltage at the pad during the receive mode.

Abstract: An integrated circuit includes a plurality of N wells disposed on a P substrate. A plurality of tap columns is located across the plurality of N wells and a plurality of standard cells is located between the tap columns. A plurality of tap cells is disposed consecutively in the plurality of tap columns. Each tap cell further includes a first tap active and a second tap active. The first tap active of a first tap cell extends to the first tap active of a second tap cell which further extends to a well boundary of either the first tap cell or the second tap cell. The first tap active of the first tap cell and the first tap active of the second tap cell are adjacent to each other in the tap column.

Abstract: A PLC network system and method operative with OFDM for generating MIMO frames with suitable preamble portions configured to provide backward compatibility with legacy PLC devices and facilitate different receiver tasks such as frame detection and symbol timing, channel estimation and automatic gain control (AGC), including robust preamble detection in the presence of impulsive noise and frequency-selective channels of the PLC network. A PLC device may include a delayed correlation detector and a cross-correlation detector operating in concert to facilitate preamble detection in one implementation.

Abstract: A method for uplink (UL) wireless backhaul communication at a wireless backhaul remote unit in a radio access network comprising receiving a configuration for radio frames and a transmission schedule through a downlink (DL) physical layer broadcast channel, wherein the transmission schedule comprises a transmission allocation for the remote unit, generating a UL data frame, wherein generating the UL data frame comprises performing forward error correction (FEC) encoding on a data bit stream to generate a plurality of FEC codewords, wherein performing the FEC encoding comprises performing Reed Solomon (RS) encoding on the data bit stream to generate a plurality of RS codewords, performing byte interleaving on the RS codewords, and performing Turbo encoding on the byte interleaved RS codewords to generate one or more Turbo codewords, wherein each Turbo codeword is encoded from more than one RS codeword, and transmitting the UL data frame according to the transmission allocation.