Abstract: In accordance with the teachings of one embodiment of the present disclosure, a method for manufacturing a semiconductor device includes forming a support structure outwardly from a substrate. The support structure has a first thickness and a first outer sidewall surface that is not parallel with the substrate. The first outer sidewall surface has a first minimum refractive index. A first anti-reflective layer is formed outwardly from the support structure and outwardly from the substrate. A second anti-reflective layer is formed outwardly from the first anti-reflective layer. The first and second anti-reflective layers each includes respective compounds of at least two elements selected from the group consisting of: silicon; nitrogen; and oxygen.

Abstract: An improved alignment structure for photolithographic pattern alignment is disclosed. A topographical alignment mark in an IC under a low reflectivity layer may be difficult to register. A reflective layer is formed on top of the low reflectivity layer so that the topography of the alignment mark is replicated in the reflective layer, enabling registration of the alignment mark using common photolithographic scanners and steppers. The reflective layer may be one or more layers, and may be metallic, dielectric or both. The reflective layer may be global over the entire IC or may be local to the alignment mark area. The reflective layer may be removed during subsequent processing, possibly with assist from an added etch stop layer, or may remain in the completed IC. The disclosed alignment mark structure is applicable to an IC with a stack of ferroelectric capacitor materials.

Abstract: An apparatus is provided. The apparatus generally comprises a photoreceptive region and a circuit region formed in a substrate. A multilayer wiring region is then formed on the substrate over at least a portion of the circuit region. The multilayer wiring region includes a wiring layer and a light-blocking layer. The wiring layer is coupled to the circuit region, and the light-blocking wall has a metal layer that is arranged along at least a portion of the perimeter of the photoreceptive region and that is formed in the same process step as the wiring layer.

Abstract: A computer system is provided that can realize polling without increasing the processing burden on the processor. Data is read by a polling unit during a prescribed period from a prescribed address in the address space. Then, if the read data satisfies a prescribed condition, an interrupt signal is generated in the polling unit. Since processor can receive the interrupt from hardware instead of performing polling with firmware, the processing burden on processor 10 can be significantly reduced.

Abstract: In a burn-in test configuration wherein a chip board having a plurality of semiconductor chips engages a heat sink board having a plurality of heat sinks. When the boards are operationally engaged, the each semiconductor chip has a heat sink has heat sink spring-loaded against the semiconductor chips. Posts coupled to one board engage posts located on the second board. The engagement of the posts orients and secures the relative positions of the two boards. A clip is provided that secures the relative position of the two boards when the two sets of posts are engaged. To uncouple the two boards, a pressure on the side of the clip permits the two boards to separate.

Abstract: An AC generator has a first terminal coupled through an Isolation Loss Detect (ILD) capacitor to the positive bus of a Power-Over-Ethernet (POE) system, and has a second terminal coupled through the primary of a transformer to earth ground. AC current flowing between ground and the positive bus causes a corresponding AC voltage across the secondary of this transformer. The secondary of the transformer is coupled to an AC detector, whose output is coupled to a comparator. The threshold of the comparator is set such that when AC current through the ILD capacitor exceeds a threshold value, an ISOLATION FAULT output is generated by the comparator.

Abstract: Layered (embedded) code-excited linear prediction (CELP) speech encoders/decoders with adaptive plus algebraic codebooks applied in each layer with fixed codebook pulses of one layer used in higher layers. Pulse weightings emphasize lower layer pulses relative to the higher layer pulses.

Abstract: A system and methods for the evaluation of the integrity of a wafer cassette and the disposition thereof are based upon evaluation of wafer measurement data obtained using a wafer sorter cassette mapping system utilized in-line during wafer sorting operations. In one embodiment, wafers are placed into slots in the wafer cassette. A wafer sorter cassette mapping sensor is scanned over the wafers in the wafer cassette. The positions of the wafers are measured while scanning the sensor over the wafers. The wafer position measurements are evaluated using a modeling system to determine slot positions, and a determination of the integrity of the cassette is generated. If the integrity determination indicates that the cassette is deformed beyond a predetermined value, the cassette is replaced. The measurement data may be stored in a data base for further trend analysis or for replacement forecasting.

Abstract: A comparator (12A,12B) includes a first differential input stage (10) including first (MN2) and second (MN3) input transistors and a load (MP9,MP10), the first input transistor (MN2) having a gate, source, and drain coupled to a first input voltage (Vin?), a first tail current source, and the load, respectively. The second input transistor has a gate and source coupled to a second input voltage (Vin+) and a first tail current source. A second differential input stage (11) includes a third (MN4) and fourth (MN5) input transistors, the third input transistor having a gate and source coupled to a first reference voltage (Vref+) and the second tail current source, respectively. The fourth input transistor (MN5) has a gate and a source coupled to a second reference voltage (Vref?) and the second tail current source, respectively. Drains of the third and fourth input transistors are coupled to the load.

Abstract: Automating optimal placement of macro-blocks in the design of an integrated circuit. A first set of placements is generated and corresponding measures of optimalness for each placement is computed. A new set of placements is generated, with each placement being generated from multiple (“chosen placements”) of the first set of placements. The position of each macro in the new placement is made to be at least substantially identical to the position of the corresponding macro in one of the chosen placements. The placements having high values of optimalness are selected to be the chosen placements, thereby causing the properties of desirable placements to be propagated to new set of placements, as is common in genetic evolution. Another aspect of the present invention enables automatic removal of overlaps in a placement.

Abstract: A system comprising a processor core adapted to execute software code and a trace logic coupled to the processor core and comprising a storage. The storage comprises at least one bit that indicates a condition and status information. The trace logic generates a trace information stream associated with the processor core as the core executes the software code. If the condition is satisfied, the trace logic adjusts a status of the trace stream in accordance with the status information.

Abstract: A control circuit for a polarity inverting buck-boost DC-DC converter, includes an operational trans-conductance amplifier that has inputs to which a sensed voltage difference signal is applied and an output connected to an input of a voltage-to-duty-cycle converter. A compensation capacitance is connected between the output of the amplifier and a fixed supply terminal. The compensation capacitance includes a first capacitor that is permanently connected between the output of the amplifier and the fixed supply terminal and a second capacitor that has a switched connection between the output of the amplifier and the fixed supply terminal. The first capacitor has a small capacitance compared to the second capacitor. The switched connection of the second capacitor is controlled by a continuous-discontinuous mode detection circuit.

Abstract: Example low-delay complementary metal-oxide semiconductor (CMOS) to emitter-coupled logic (ECL) converters, methods and apparatus are disclosed. A disclosed example apparatus includes a reference level generator circuit to generate first and second reference signals and a bias signal based on a CMOS supply voltage, a source follower circuit to convert a CMOS input signal to a single-ended ECL signal based on the first and second reference signals, and an ECL buffer circuit to convert the single-ended ECL signal to a differential ECL output signal based on the bias signal and an ECL supply voltage.

Abstract: A combination pivoting mirror and support bracket has a bracket for supporting a pivoting mirror assembly and for attaching the combination to a using device. The bracket has first and second edges. A first portion of the bracket defines a mounting area for fixedly securing the first portion to the using device, and a second portion of the bracket is for mounting the pivoting mirror. An isolation slot is formed in the bracket and located between the first portion of the bracket and the second portion of the bracket. A plurality of piezoelectric devices are mounted to the second portion of the bracket and extend substantially orthogonal to a surface of the bracket. A pivoting mirror has a pair of torsional hinges for pivotally supporting a reflective surface. Each hinge of the pair extends away from the reflecting surface and along a selected axis to an anchor portion.

Abstract: Measurements of parameters of MOS transistors, also known as MOSFETs, such as threshold potentials, require accurate estimates of source and drain series resistance. In cases where connections to the MOSFET include significant external series resistance, as occurs in probing transistors that are partially fabricated or deprocessed, accurate estimates of external resistances are also required. This invention comprises a method for estimating series resistances of MOSFETs, including resistances associated with connections to the MOSFET, such as probe contacts. This method is applicable to any MOSFET which can be accessed on source, drain, gate and substrate terminals, and does not require other test structures or special connections, such as Kelvin connections.

Abstract: A digital storage element (e.g., a flip-flop or a latch) includes a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to the master transparent latch. The slave transparent latch includes dedicated functional data and scan data output ports. The digital storage element operates in a functional mode and in a scan mode. While in the scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch. The first and second clock signals are non-overlapping and, as such, avoid the digital storage element from creating hold violations.

Abstract: A capacitor (100) is disclosed that is formed as part of an integrated circuit (IC) fabrication process. The capacitor (100) has conductive top and bottom electrodes (140, 144) and a nonconductive capacitor dielectric (142). In one example, the dielectric (142) includes first and second thin dielectric layers (112, 114) that sandwich a layer of antireflective material (118). The thin layers (112, 114) provide the dielectric behavior necessary for the capacitor while the antireflective layer (118) promotes reduced feature sizes by mitigating reflected standing waves, among other things.

Abstract: The invention relates to an integrated electronic device for digital signal processing, which includes a phase locked loop for generating an output clock signal based on a reference clock input signal, multiple outputs for providing multiple representatives of the output clock signal, a stage for generating a phase shifted output clock signal having multiple phases spanning one clock period of the output clock signal, a register having multiple units each coupled by a data input to a representative of the output clock signal, and to the phase shifted output clock signal for storing single bit values in response to an edge of the shifted output clock signal, wherein the stage for generating the phase shifted output clock is controlled to selectively shift the phase of the output clock and circuitry for reading out the stored single bit values from the register is provided in order to determine the output skew of the output clock signals based on the read out single bit value.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefore and an integrated circuit including the same. The semiconductor device (300), without limitation, may include a gate electrode (320) having a gate length (l) and a gate width (w) located over a substrate (310) and a gate electrode material feature (330) located adjacent a gate width (w) side of the gate electrode (320). The semiconductor device (300) may further include a silicide region (350) located over the substrate (310) proximate a side of the gate electrode (320), the gate electrode material feature (330) breaking the silicided region (350) into multiple silicide portions (353, 355, 358).

Abstract: A feedback loop in a variable power supply has an adjustable response speed based on operating conditions of the power supply. The response speed can be increased upon encountering a transient to improve response performance to the transient. A response speed control for the control loop modifies or bypasses a major low frequency pole in a compensation network in the control loop to increase response speed. The control limits fast response duration or impact with respect to the low frequency pole to avoid instability issues. The control may include counters or timers to selectively disable or enable the fast response function. The control can operate based on an error feedback signal and a reference to determine when a fast response should be applied. The resulting power supply system provides robust, well-regulated power, with fast responses to system transients.