Abstract: The present invention provides a distributed element generator for use with an electronic design automation tool. In one embodiment, the distributed element generator includes a parasitic element extractor configured to identify parasitic elements associated with a passive integrated circuit device having a surrounding layout environment. Additionally, the distributed element generator also includes a distributed parameter allocator coupled to the parasitic element extractor and configured to provide a distributed model of the passive integrated circuit device and allocate the parasitic elements within the distributed model based on the surrounding layout environment.

Abstract: A system and method is provided for providing integrated over-current protection in a switching power supply. In one embodiment, a switching power supply could comprise a gate drive circuit operative to receive a pulse-width modulated (PWM) signal and to drive at least one power field effect transistor (FET) between alternating activated and deactivated states based on a pulse-width of the PWM signal. The switching power supply could also comprise a current sense circuit operative to measure a current associated with the at least one power FET during the activated state. The switching power supply could also comprise a first over-current protection circuit providing a first adjustment to the PWM signal in response to the current being substantially between a first threshold and a second threshold. The second threshold could be greater than the first threshold.

Abstract: A display system for creating a full-color projected image. Light from a white light source passes through a color modulator (106). The color modulator (106) is a stack of at least two dielectric layers exposed to an electric field. The applied electric field operates to change the index of refraction of the dielectric material enough to cause the stack of dielectric layers to selectively reflect or transmit various wavelength bands. By changing the electric field, the color modulator (106) provides a series of three primary color light beams that are modulated by a spatial light modulator (112). A controller (128) controls the operation of the spatial light modulator (112) to form an image bearing beam of primary colored light. The image bearing beam of light is focused onto an image plane by a projection optics (124).

Abstract: In one embodiment, a switching regulator comprises a control circuit that activates and deactivates at least one power switch to control a voltage of a switching node. The system also comprises an inductor that conducts a current from the switching node to an output to generate an output voltage. The system further comprises a PWM comparison circuit that controls an on-time and/or an off-time of the at least one power switch based on a comparison of a feedback voltage and a reference voltage. The PWM comparison circuit comprises a ramp signal generator configured to provide a ramp signal having a non-zero slope that is combined with either the feedback voltage or the reference voltage at a beginning of either the on-time or the off-time. The PWM comparison circuit can be further configured to set the slope of the ramp signal to zero during the off-time in a discontinuous conduction mode.

Abstract: An ESD protection circuit is designed on an integrated circuit (100) having a first power supply bus (106) and a second power supply bus (108). The circuit includes a first logic gate (116, 118) having a current path coupled to the first power supply bus. The first logic gate includes an output terminal. A second logic gate (122, 124) has a current path coupled to the second power supply bus. The second logic gate has an input terminal coupled to the output terminal of the first logic gate. A first device (306) is coupled in series with the current path of the second logic gate and is always on during normal circuit operation.

Abstract: An offset correction circuit examines a residue signal of a stage of a pipeline analog to digital converter (ADC) to determine whether a parameter which could cause offset error, needs to be adjusted. In an embodiment, the parameter is adjusted until a maximum range of the residue signal equals an expected range. In the described examples, the adjusted parameters include timing offset error (when components of an ADC sample the input signal at different time instances) and a voltage offset error (the threshold voltage at which a sub-ADC in a stage the generated sub-code changes to a next value).

Abstract: A semiconductor integrated circuit equipped with multiple serially coupled scan chains which are used to shift inspection data based on different clock signals in order to inspect a scan path is provided. Inspection data is supplied to the respective scan chains in a first inspection mode, and the inspection data is supplied to the first stages of scan chains when in a second inspection mode. The inspection data supplied to the serially coupled scan chains in the second inspection mode is held in sequence by data hold units while being shifted between the scan chains.

Abstract: In accordance with the teachings of the present invention, a system and method for local value adjustment are provided. In one embodiment, the method includes identifying a hue, saturation, and brightness value for each pixel of an image, determining whether the hue and saturation for each pixel fall within a first predetermined set of hue and saturation combinations, determining whether the brightness value for each pixel of the image falls within a predetermined set of brightness values, and selectively applying a gain to the saturation of each pixel based upon the determination of whether the hue and saturation value of the pixel falls within the first predetermined set of hue and saturation combinations and the determination of whether the brightness value of the pixel falls within the predetermined set of brightness values.

Abstract: Method for dynamically compensating probe tip misalignment with a semiconductor wafer. The wafer is located on a handler and the wafer is adjusted to a first temperature. Probe tips of an inspection system are moved to a first position centered above pads of a test module on the wafer. The first position is recorded in a memory of the inspection system at the first temperature. The wafer and the probe tips are adjusted to a second temperature while the wafer remains in the inspection system. A second position of the probe tips is recorded in the memory while the probe tips and the wafer are equilibrated at the second temperature. A difference between the first and second position is calculated. Relative positions of the probe tips or the wafer is compensated based on the calculated difference, such that the probe tips are re-centered above the pads at the second temperature.

Abstract: Embodiments of the present disclosure provide a reporting allocation unit, an indicator interpretation unit and methods of operating a reporting allocation unit and an indicator interpretation unit. In one embodiment, the reporting allocation unit includes an indicator configuration module configured to provide reporting interval and offset values of corresponding rank and channel quality indicators for user equipment. The reporting allocation unit also includes a sending module configured to transmit the reporting interval and offset values to the user equipment.

Abstract: A DC-DC boost converter is provided that generally maintains discontinuous mode operation in a generally efficient manner. To accomplish this, a clamp generator, comparator, logic gates, a flip-flop, and counter are employed. These components generally operate together to determine if an over-limit condition has taken place, so that the ON time of the boost converters' switch can be varied accordingly.

Abstract: An apparatus, an integrated controller and a method of securely supplying goods to a customer. In one embodiment, the apparatus includes: (1) a chassis having a first compartment configured to store goods at a first temperature and a second compartment configured to store goods at a second temperature different from the first temperature, (2) an access barrier mounted to the chassis and movable between an open position in which access to the first and second compartments is allowed and a closed position in which the access is denied and (3) an integrated controller including an access management system configured to control the access to the first and second compartments through the access barrier and a goods management system configured to track goods deposited to and retrieved from the first and second compartments.

Abstract: An RSS indicator with a linear characteristic that is of a simple configuration, low current consumption and small die area requirements, comprises a pair of input transistors with coupled emitters and base electrodes to which an input signal is differentially applied. Each of the input transistors has a collector load circuit connected between a first supply terminal and its collector, and a tail current sink connected between a second supply terminal and the coupled emitters. The load circuit of each input transistor includes a current source which supplies a current copied from the tail current. A signal strength indicator signal is obtained from a differential signal between corresponding output nodes of the collector load circuits by taking the mean value of the differential signal referenced to the first supply terminal.

Abstract: Emulation information including emulation control information and emulation data is exported from a data processor by arranging the emulation information into information blocks, and outputting a sequence of the information blocks from the data processor. Some of the information blocks of the sequence have relative proportions of emulation control information and emulation data that differ from the relative proportions of emulation control information and emulation data in other blocks of the sequence.

Abstract: This invention modifies Viterbi decoding to improve BER. Within the state metric unit cascade block, this invention forces the unused ACS units decision bits to a 0 for the top rail and a 1 for the bottom rail. This invention modifies the final maximum state index with the selected decision bits from the unused ACS units. This invention uses the modified final maximum state index as the initial conditions for the k?1 traceback shift register. This invention also uses the final maximum state index to mask the generated pretraceback decision bits generated from the last block of ACS units.

Abstract: Apparatus to compare an input signal to a threshold level are disclosed. An example circuit described herein includes a Widlar bandgap circuit to receive the input signal, an intermediate stage coupled with the output of the Widlar bandgap circuit, and a final stage coupled with the output of the intermediate stage, the final stage to provide an output based on the input signal and the threshold level.

Abstract: The present invention provides a system for dissipating any aberrant charge that may accumulate during the fabrication of a semiconductor device segment (200), obviating overstress or break down damage to a focal device structure (208) that might result from uncontrolled dissipation of the aberrant charge. A substrate (202) has first and second intermediate structures (204, 206) disposed atop the substrate, with the focal structure disposed atop the substrate therebetween. A first conductive structure (210) is disposed atop the second intermediate structure, the focal structure, and a portion of the first intermediate structure. A third intermediate structure (214) is disposed contiguously atop the first conductive structure and the first intermediate layer. A void (216) is formed in a peripheral region (218) of device segment, through the first and third intermediate layers down to the substrate.

Abstract: A differential amplifier includes a differential input pair (2A) coupled to a folded cascode stage (2B) and a common mode feedback circuit (34) including a tracking circuit (30A) coupled to first (Vout?) and second (Vout+) outputs of the folded cascode stage (2B). The first and second outputs are coupled to first terminals of first (31A) and second (31B) tracking capacitors which have second terminals on which a first common mode output signal (VCM1) is produced and also are coupled to first terminals of third (32A) and fourth (32B) tracking capacitors, respectively, which have second terminals on which a second common mode output signal (VCM2) is produced. The first and third tracking capacitors are discharged by first (27A) and second (27B) switches that directly couple the first and second outputs to first and second inputs of a common mode feedback amplifier (4). A desired common mode output voltage (VCM-IN) is applied to a third input of the common mode feedback amplifier.

Abstract: A digital video acquisition system including a plurality of image processors (30A; 30B) is disclosed. A CCD imager (22) presents video image data on a bus (video_in) in the form of digital video data, arranged in a sequence of frames. A master image processor (30A) captures and encodes a first group of frames, and instructs a slave image processor (30B) to capture and encode a second group of frames presented by the CCD imager (22) before the encoding of the first group of frames is completed by the master image processor. The master image processor (30A) completes its encoding, and is then available to capture and encode another group of frames in the sequence. Video frames that are encoded by the slave image processor (30B) are transferred to the master image processor (30A), which sequences and stores the transferred encoded frames and also those frames that it encodes in a memory (36A; 38).

Abstract: Compensation is provided for signal drop in bond wires of an integrated circuit (IC) while minimizing the number of external terminals in the IC package. A functional circuit provides an output signal (e.g., voltage) on a pad of the IC, which is connected to an external terminal on the package via a bond wire. A second circuit contained in the IC determines the signal drop in the bond wire by examining a parameter (e.g., current) proportional to a strength of the output signal at or before the pad in a transmission path of the signal. Thus, additional external terminals to sense the signal strength at a point external to the IC to provide compensation for the drop may not be required.