Abstract: A semiconductor device includes one or more LDMOS transistors and one of more SCR-LDMOS transistors. Each LDMOS transistor includes a LDMOS well of a first conductivity type, a LDMOS source region of a second conductivity type formed in the LDMOS well, and a LDMOS drain region of a second conductivity type separated from the LDMOS well by a LDMOS drift region of the second conductivity type. Each SCR-LDMOS transistor comprising a SCR-LDMOS well of the first conductivity type, a SCR-LDMOS source region of the second conductivity type formed in the SCR-LDMOS well, a SCR-LDMOS drain region of a second conductivity type, and a anode region of the first conductivity type between the SCR-LDMOS drain region and the SCR-LDMOS drift region. The anode region is separated from the SCR-LDMOS well by a SCR-LDMOS drift region of the second conductivity type.
Type:
Grant
Filed:
February 21, 2005
Date of Patent:
August 19, 2008
Assignee:
Texas Instruments Incorporated
Inventors:
Sameer P. Pendharkar, Jonathan S. Brodsky
Abstract: A closed loop amplifier adapted to be directly connected to a battery having a battery voltage for powering the amplifier. The amplifier includes an amplifier stage having a node for receiving a control voltage for controlling a common mode voltage of the stage, a digital voltage indicator for generating a digital value corresponding to the battery voltage, and a common mode voltage supply providing the control voltage corresponding to the digital value.
Type:
Grant
Filed:
June 6, 2006
Date of Patent:
August 19, 2008
Assignee:
Texas Instruments Incorporated
Inventors:
Jagadeesh Krishnan, Srinath M Ramaswamy, Gangadhar Burra
Abstract: A digital device 310 with a plurality of collocated wireless networks encounters inter-network interference if the collocated wireless networks operate in a common operating frequency. A coordinator unit 510, coupled to the plurality of wireless networks, provides a transmission reservation system wherein a wireless network with a need to transmit can request and receive a reservation for time to transmit. The coordinator unit 510 provides a way to schedule transmissions from the plurality of wireless networks and to reduce the probability of collisions.
Abstract: A pivoting device such as a MEMS mirror provides improved coupling between a permanent magnet on the device and an adjacent electrical coil that may provide a drive force or position sensing. The improved coupling is obtained by forming a cavity in the coil structure. The cavity receives the permanent magnet such that the spacing between the magnet and the electrical windings or coil is at a minimum.
Abstract: A semiconductor device has a leadframe with a structure made of a base metal (105), wherein the structure consists of a chip mount pad (302) and a plurality of lead segments (303). Covering the base metal are, consecutively, a continuous nickel layer (201) on the base metal, a layer of palladium on the nickel, wherein the palladium layer (203) on the chip side of the structure is thicker than the palladium layer (202) opposite the chip, and a gold layer (204) on the palladium layer (202) opposite the chip. A semiconductor chip (310) is attached to the chip mount pad and conductive connections (312) span from the chip to the lead segments. Polymeric encapsulation compound (320) covers the chip, the connections, and portions of the lead segments, but leaves other segment portions available for solder reflow attachment to external parts.
Abstract: The present invention provides method of manufacturing a metal-insulator-metal capacitor (100). A method of manufacturing includes depositing a first refractory metal layer (105) over a semiconductor substrate (110). The first refractory metal layer (105) over a capacitor region (200) of the semiconductor substrate (110) is removed and a second refractory metal (300) is deposited over the capacitor region (200). Other aspects of the present invention include a metal-insulator-metal capacitor (900) and a method of manufacturing an integrated circuit (1000).
Abstract: The present invention provides a method for analyzing critical defects in analog integrated circuits. The method for analyzing critical defects, among other possible steps, may include fault testing a power field effect transistor (120) portion of an analog integrated circuit (115) to obtain electrical failure data. The method may further include performing an in-line optical inspection of the analog integrated circuit (115) to obtain physical defect data, and correlating the electrical failure data and physical defect data to analyze critical defects.
Type:
Grant
Filed:
January 31, 2005
Date of Patent:
August 19, 2008
Assignee:
Texas Instruments incorporated
Inventors:
Martin B. Mollat, Milind V. Khandekar, Tony T. Phan, Kyle M. Flessner
Abstract: One aspect of the invention provides an integrated circuit (IC). The IC comprises transistors and contact fuses. The contact fuses each comprise a conducting layer, a frustum-shaped contact has a narrower end that contacts the conducting layer and a first metal layer that is located over the conducting layer. A wider end of the frustum-shaped contact contacts the first metal layer. The frustum-shaped contact has a ratio of an opening of the wider end to the narrower end that is at least about 1.2. The contact fuses each further include a heat sink that is located over and contacts the first metal layer.
Type:
Grant
Filed:
April 25, 2006
Date of Patent:
August 19, 2008
Assignee:
Texas Instruments Incorporated
Inventors:
Honglin Guo, Dongmei Lei, Brian Goodlin, Joe McPherson
Abstract: The present invention provides a photoresist removal process and a method for manufacturing an interconnect using the same. One embodiment of the photoresist removal process includes, among other steps, providing a low dielectric constant (k) substrate having a photoresist layer located thereover, and removing the photoresist layer using a plasma which incorporates a gas which includes hydrogen or deuterium and a small amount of oxygen less than about 20 volume percent of the gas. Another embodiment of the photoresist removal process includes, among other steps, providing a low dielectric constant (k) substrate having a photoresist layer located thereover, removing a bulk portion of the photoresist layer using a plasma which incorporates a gas which includes hydrogen or deuterium, and removing a small portion of the photoresist layer using a plasma which incorporates a gas which includes oxygen, wherein the order of the two removing steps is interchangeable.
Type:
Grant
Filed:
June 8, 2005
Date of Patent:
August 19, 2008
Assignee:
Texas Instruments Incorporated
Inventors:
Patricia Beauregard Smith, Laura M. Matz, Vinay Shah
Abstract: Manufacturing a semiconductor device by forming first and second gates including patterning a silicon-containing layer on a substrate. Etched simultaneously the patterned silicon-containing layer of the first gate, and first substrate portions adjacent to the first gate to form a first gate electrode and source and drain openings. Forming SiGe simultaneously in first gate electrode source and drain openings. Second gate and second substrate portions are masked. SiGe is removed from an upper surface of the first gate to form a second opening therein. A metal deposited on the first and second gates forms a metal layer thereon. Annealing first and second gates to form FUSI first and second gate electrodes. A metal amount at an interface of the FUSI gate electrode layer and an underlying gate dielectric layer is greater than at a second interface of the second FUSI gate electrode layer and an underlying second gate dielectric layer.
Abstract: In a method embodiment, a method for image processing includes receiving one or more signals indicative of an optical characteristic of one or more respective light beams. A transform is generated based on the received one or more signals. The transform converts a first plurality of image components encoded by a first plurality of colors to a second plurality of image components encoded by a second plurality of colors.
Abstract: The present invention provides a concurrent gain generator for use with a MIMO transmitter havi'ng an N of two or more transmit antennas. In one embodiment, the concurrent gain generator includes a first sequence formatter that provides one of the N transmit antennas with a gain training sequence during an initial time interval, and a second sequence formatter that further provides (N?1) remaining transmit antennas with (N?1) additional gain training sequences during the initial time interval to train receive gains. The present invention also provides a non-concurrent gain adjuster for use with a MIMO receiver employing an M of two or more receive antennas. In one embodiment, the non-concurrent gain adjuster includes a gain combiner that computes a common receive gain as a function of M independent receive gains, and a gain applier that applies the common receive gain to receivers associated with the M receive antennas.
Type:
Application
Filed:
April 21, 2008
Publication date:
August 14, 2008
Applicant:
Texas Instruments Incorporated
Inventors:
Manish Goel, David P. Magee, Michael T. DiRenzo, Michael O. Polley
Abstract: A circuit producing a reversed bandgap reference voltage circuit VRBG includes first and second resistors coupled as a voltage divider between ground and a first conductor, a base of a first transistor being coupled to the voltage divider to produce a first voltage VBE1(1+1/M) between the first conductor and ground, M being a ratio of the resistances of the first and second resistors. A third resistor is coupled between a base of the second transistor and ground to produce a second voltage VBE2+VRBGP between the second conductor and ground. First circuitry forces the collector current of the first transistor to be equal to the collector current of the second transistor, and second circuitry forces the first voltage VBE1(1+1/M) to be equal the second voltage VBE2+VRBGP. One of the first circuitry and second circuitry includes an operational amplifier coupled to effectuate the forcing.
Type:
Grant
Filed:
June 22, 2006
Date of Patent:
August 12, 2008
Assignee:
Texas Instruments Incorporated
Inventors:
Vadim Valerievich Ivanov, Keith Eric Sanborn
Abstract: The invention provides systems, devices, and methods for frequency hopping. In one method embodiment, the invention hops between frequencies by using the same channel to transmit data from a master to a slave, and from the slave to the master. One system embodiment provides an enhanced master coupled to an enhanced slave. In one device embodiment, the invention is a computer readable medium adapted to enable frequency hopping in a frequency band.
Abstract: An amplifier includes first and second pairs of differentially coupled input transistors. The first current mirror generates a reference current which is mirrored by a second current mirror to produce a mirrored reference current. Current steering circuitry steers the mirrored reference current as a first tail current through the first pair when a common mode voltage associated with a differential input voltage exceeds a first reference voltage. A first portion of the mirrored reference current flows from the first current steering circuitry when the common mode voltage is greater than the first reference voltage to produce a second tail current for the second pair. A second portion of the mirrored reference current is fed back to an output of the first current mirror and summed with the reference current so as to reduce the second portion when the common mode voltage is greater than the first reference voltage.
Abstract: Phosphonate surfactants are employed to passivate the surfaces of MEMS devices, such as digital micromirror devices. The surfactants are adsorbed from vapor or solution to form self-assembled monolayers at the device surface. The higher binding energy of the phosphonate end groups (as compared to carboxylate surfactants) improves the thermal stability of the resulting layer.
Type:
Grant
Filed:
January 5, 2005
Date of Patent:
August 12, 2008
Assignee:
Texas Instruments Incorporated
Inventors:
Simon Joshua Jacobs, Seth Adrian Miller
Abstract: A method (10) of forming fully-depleted silicon-on-insulator (FD-SOI) transistors (150) and partially-depleted silicon-on-insulator (FD-SOI) transistors (152) on a semiconductor substrate (104) as part of an integrated circuit fabrication process is disclosed.
Abstract: An amplifier circuit includes an pair of input transistors, the drains of which are connected to emitters of first and second cascode transistors. First and second controlled current sources are connected to the emitters of the first and second cascode transistors, respectively, and third and fourth controlled current sources are connected to the collectors thereof. A bias circuit controls the 4 controlled current sources in response to the emitter voltage of a pair of input transistors of an output stage the inputs of which are connected to the drains of the first and second cascode transistors.
Abstract: A micromirror array 110 fabricated on a semiconductor substrate 11. The array 110 is comprised of four operating layers 12, 13, 14, 15. An addressing layer 12 is fabricated on the substrate. A raised electrode layer 13 is spaced above the addressing layer by an air gap. A hinge layer 14 is spaced above the raised electrode layer 13 by another air gap. A mirror layer 15 is spaced over the hinge layer 14 by a third air gap.
Abstract: An apparatus for regulating a switching device that couples an output locus with one of a first voltage locus and a second voltage locus in response to a driver unit includes: a voltage feedback unit coupling the driver unit with at least one of the first voltage locus and the second voltage locus. The feedback unit provides a voltage feedback signal to the driver unit. The driver unit responds to the voltage feedback signal to affect the coupling by the switching device.
Type:
Grant
Filed:
July 27, 2005
Date of Patent:
August 12, 2008
Assignee:
Texas Instruments Incorporated
Inventors:
Patrick Muggler, David John Baldwin, Roy Clifton Jones, III