Abstract: A semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the buried layer. A fourth lightly doped region (400) having the second conductivity type is formed between the second lightly doped region and the buried layer.

Abstract: A wireless device includes a preamble detector configured to identify preambles transmitted via a random access channel of a wireless network. The preamble detector includes preamble false alarm logic. The preamble false alarm logic is configured to set a preamble false alarm detection window, and compare, to one another, preambles identified in the false alarm detection window. The preamble false alarm logic is configured to identify, based on the comparison, a largest of the preambles in the false alarm detection window, and reject all but the identified largest of the preambles as false alarm detections.

Abstract: Relaxation oscillator circuitry is presented with low drift and native offset cancellation, including an amplifier amplifying a first current signal to provide a pulse amplifier output waveform, an integrator integrating a second current signal to provide a ramp output waveform, and a comparator comparing the integrator output waveform with a threshold set by the amplifier output waveform to generate an alternating oscillator output used to switch the polarities of the first and second current signals.

Abstract: Methods for testing an application specific integrated circuit (ASIC). A set of representations is created that overlays power density information and clock gate physical locations of a set of clock gates in a critical sub-chip of the ASIC for test mode power analysis. The set of representations are further grouped in the sub-chip into various groups based on overlapping of the set of representations. Then, a set of test control signals is generated corresponding to each of the set of clock gates during at-speed test mode of operation such that each clock gate with overlapping representations receive different test control signals. Further, patterns are generated using a virtual constraint function to selectively enable the set of test control signals such that the set of test control signals are not activated simultaneously.

Abstract: A leadframe (300) for use in semiconductor devices, comprising an assembly pad (3010 having rectangular sides, the pad extending, on one pad side (301b), into a lead (302) and, on the opposite pad side (301a), into straps (350) oriented normal to the side (301a) and anchored in adjacent tie bars (313), strap surfaces having recesses (501, 502) suitable for interlocking with packaging materials. The leadframe further includes a plurality of leads (303) parallel to and alternating with the straps.

Abstract: A method of testing semiconductor devices includes contacting bond pads coupled to integrated circuitry on a first die of a plurality of interconnected die on a substrate using a probe system having probes and probe tests including parametric tests, continuity tests, and a kill die subroutine. Probe tests using the probe program are performed. Die are binned into a first bin (Bin 1 die) for being a good die for all probe tests, or a second bin (Bin 2 die) for failing at least one of continuity tests and parametric tests. The Bin 2 die are divided into a first sub-group that failed the continuity tests and a second sub-group that do not fail the continuity tests. A kill die subroutine is triggered including applying power sufficient to selectively cause damage to the second sub-group of Bin 2 die to generate a continuity failure and thus generate kill die.

Abstract: A circuit that facilitates faster diagnosis of plurality of logic circuits connected in a scan chain is provided. The circuit includes a first multiplexer that receives a scan data input. A flip-flop is coupled to an output of the first multiplexer and generates a scan pattern. An inverter generates an inverted feedback signal in response to the scan pattern. The inverted feedback signal is provided to the first multiplexer. A plurality of logic circuits is connected in a scan chain and generates a logic output in response to the scan pattern. A bypass multiplexer is coupled to the plurality of logic circuits. The bypass multiplexer generates a scan output in response to the logic output, the scan data input and a segment bypass input.

Abstract: According to an aspect of present disclosure, a set of power amplifiers are used to amplify power of a signal for transmission. The signal powers from a set of power amplifiers are coupled to set of primary windings which are commonly coupled to a secondary winding such that the powers on the primary windings are additive in the secondary winding. A current path on the primary side is provided for flow of a current that is induced on at least one primary winding when a power amplifier coupled to that primary winding is in “off” state. As a result, the induced current is prevented from flowing in to the power amplifier that are in “on” state. Further, the current path isolates the power amplifiers from each other thereby enabling the power amplifiers to operate at the rated efficiency. In one embodiment, the current path is provided using a resistor network.

Abstract: A method and apparatus for executing program loops. A processor, includes an execution unit and an instruction fetch buffer. The execution unit is configured to execute instructions. The instruction fetch buffer is configured to store instructions for execution by the execution unit. The instruction fetch buffer includes a loop buffer configured to store instructions of an instruction loop for repeated execution by the execution unit. The loop buffer includes buffer control logic. The buffer control logic includes pointers, and is configured to predecode a loop jump instruction, identify loop start and loop end instructions using the predecoded loop jump instruction and pointers; and to control non-sequential instruction execution of the instruction loop. The width of the pointers is determined by loop buffer length and is less than a width of an address bus for fetching the instructions stored in the loop buffer from an instruction memory.

Abstract: An integrated circuit containing PMOS transistors may be formed by forming a dual layer hard mask. A first layer of the hard mask is halogen-containing silicon nitride formed using a halogenated silane reagent. A second layer of the hard mask is silicon nitride formed on the first layer using halogen-free reagents. After source/drain cavities are etched in the PMOS transistors, a pre-epitaxial bake with hydrogen is performed. After SiGe epitaxial source/drain regions are formed, the hard mask is removed.

Abstract: A system for controlling an epitaxial growth process in an epitaxial reactor. The system includes a processor for setting up a modeled output parameter value as a linear function of the actual output parameter value and a second set of thermocouple offset parameter values. The processor also determines a distance between a target output parameter value and the modeled output parameter value.

Abstract: A computer system includes a processor and program storage coupled to the processor. The program storage stores a software instruction translator that, when executed by the processor, is configured to receive source code and translate the source code to a low-level language. The source code is restricted to a subset of a high-level language and the low-level language is a specialized instruction set. Each statement of the subset of the high-level language directly maps to an instruction of the low-level language.

Abstract: An electronic device includes a first circuit (111) operable to generate at least a first and a second channel quality indicator (CQI) vector associated with a plurality of subbands for each of at least first and second spatial codewords respectively and generate a first and a second reference CQI for the first and second spatial codewords, and operable to generate a first and a second differential subbands CQI vector for each spatial codeword and generate a differential between the second reference CQI and the first reference CQI, and further operable to form a CQI report derived from the first and the second differential subbands CQI vector for each spatial codeword as well as the differential between the second reference CQI and the first reference CQI; and a second circuit (113) operable to initiate transmission of a signal communicating the CQI report. Other electronic devices, processes and systems are also disclosed.

Abstract: Systems and methods for carrier sense multiple access (CSMA) protocols for power line communications (PLC) are described. In some embodiments, a method may include performing a virtual carrier sensing operation and, in response to the virtual carrier sensing operation indicating that a communication channel is idle, calculating a contention window. The method may also include performing a physical carrier sensing operation subsequent to the virtual carrier sensing operation, the physical carrier sensing operation based, at least in part, upon the contention window. In response to the physical carrier sensing operation indicating that the communication channel is idle, the method may then include transmitting data over the channel. In other embodiments, another method may include determining that a data transmission is a unicast transmission and that an acknowledgement message has not been received.

Abstract: A phase locked loop circuit (30, 100, 110) includes a controllable oscillator (42) for generating an output signal of desired frequency responsive to a control signal, a first phase detection circuit (32, 102, 112) for generating an output indicative of phase differential responsive to the output signal and a first edge of a reference signal and a second phase detection circuit (34, 104, 114) for generating an output indicative of phase differential responsive to the output signal and a second edge of a reference signal. The control signal to the controllable oscillator (42) is driven by the outputs of the first and second phase detections circuits.

Abstract: A method for forming MOS transistor includes providing a substrate including a semiconductor surface having a gate electrode on a gate dielectric thereon, dielectric spacers on sidewalls of the gate electrode, a source and drain in the semiconductor surface on opposing sides of the gate electrode, and a pre-metal dielectric (PAD) layer over the gate electrode and over the source and drain regions. Contact holes are formed through the PMD layer to form a contact to the gate electrode and contacts to the source and drain. A post contact etch dielectric layer is then deposited on the contacts to source and drain and on sidewalls of the PMD layer. The post contact etch dielectric layer is selectively removed from the contacts to leave a dielectric liner on sidewalls of the PMD layer. A metal silicide layer is formed on the contacts to the source and drain.

Abstract: Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.

Abstract: Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.

Abstract: An integrated circuit containing an SAR SRAM and CMOS logic, in which sidewall spacers on the gate extension of the SAR SRAM cell are thinner than sidewall spacers on the logic PMOS gates, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively etch the sidewall spacers on the on the gate extension of the SAR SRAM cell, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively implanting extra p-type dopants in the drain node SRAM PSD layer, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact.

Abstract: An integrated circuit may be formed by removing source/drain spacers from offset spacers on sidewalls of MOS transistor gates, forming a contact etch stop layer (CESL) spacer layer on lateral surfaces of the MOS transistor gates, etching back the CESL spacer layer to form sloped CESL spacers on the lateral surfaces of the MOS transistor gates with heights of ¼ to ¾ of the MOS transistor gates, forming a CESL over the sloped CESL spacers, the MOS transistor gates and the intervening substrate, and forming a PMD layer over the CESL.