Abstract: Systems and methods for carrier sense multiple access (CSMA) protocols for power line communications (PLC) are described. In some embodiments, a method may include performing a virtual carrier sensing operation and, in response to the virtual carrier sensing operation indicating that a communication channel is idle, calculating a contention window. The method may also include performing a physical carrier sensing operation subsequent to the virtual carrier sensing operation, the physical carrier sensing operation based, at least in part, upon the contention window. In response to the physical carrier sensing operation indicating that the communication channel is idle, the method may then include transmitting data over the channel. In other embodiments, another method may include determining that a data transmission is a unicast transmission and that an acknowledgement message has not been received.

Abstract: Systems and methods for cell anomaly detection are provided. The disclosed systems and methods of cell anomaly detection may use a single circuit to detect both cell-open and imbalance conditions. Disclosed embodiments may incorporate a continuous or a sampled time system (i.e. cell anomaly detection is performed when an enable signal is active). An example embodiment includes receiving voltages of a plurality of cells of a battery pack; converting the received voltages to currents; determining a maximum current of the currents; determining whether at least one of the currents is anomalous; and reporting the at least one anomalous current as indicative of a bad cell.

Abstract: A semiconductor device includes a depletion mode GaN FET and an integrated driver/cascode IC. The integrated driver/cascode IC includes an enhancement mode cascoded NMOS transistor which is connected in series to a source node of the GaN FET. The integrated driver/cascode IC further includes a driver circuit which conditions a gate input signal and provides a suitable digital waveform to a gate node of the cascoded NMOS transistor. The cascoded NMOS transistor and the driver circuit are formed on a same silicon substrate.

Abstract: An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is epitaxially formed in the source/drain regions, so that that a top edge of the SiGe semiconductor material at the field oxide does not extend more than one third of a depth of the SiGe in the source/drain region abutting the field oxide. Dielectric spacers on lateral surfaces of the gate structure on the field oxide extend onto the SiGe; at least one third of the SiGe is exposed. Metal silicide covers at least one third of a top surface of the SiGe. A contact has at least half of a bottom of the contact directly contacts the metal silicide on the SiGe.

Abstract: A system for controlling an epitaxial growth process in an epitaxial reactor. The system includes a processor for setting up a modeled output parameter value as a linear function of the actual output parameter value and a second set of thermocouple offset parameter values. The processor also determines a distance between a target output parameter value and the modeled output parameter value.

Abstract: An integrated circuit may be formed by removing source/drain spacers from offset spacers on sidewalls of MOS transistor gates, forming a contact etch stop layer (CESL) spacer layer on lateral surfaces of the MOS transistor gates, etching back the CESL spacer layer to form sloped CESL spacers on the lateral surfaces of the MOS transistor gates with heights of ¼ to ¾ of the MOS transistor gates, forming a CESL over the sloped CESL spacers, the MOS transistor gates and the intervening substrate, and forming a PMD layer over the CESL.

Abstract: A power mode control system for microprocessors offers an unlimited variety of hardware-supported power modes that may satisfy any operating scenario. The microprocessor unit comprises a register that contains particular bit fields for defining selectable power modes. The particular bit fields in the register define pointers to a power mode defining register. Each pointer selects a corresponding bit field in the power mode defining register. The bits in the bit fields of the power mode defining register either directly control a power mode of at least one functional or peripheral blocks of the unit; or they are pointers to a further power mode defining register and the bits in the bit fields of the further power mode defining register directly control a power mode of at least one functional or peripheral blocks of the unit.

Abstract: Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.

Abstract: An integrated circuit containing an SAR SRAM and CMOS logic, in which sidewall spacers on the gate extension of the SAR SRAM cell are thinner than sidewall spacers on the logic PMOS gates, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively etch the sidewall spacers on the on the gate extension of the SAR SRAM cell, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively implanting extra p-type dopants in the drain node SRAM PSD layer, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact.

Abstract: A computer system includes a processor and program storage coupled to the processor. The program storage stores a software instruction translator that, when executed by the processor, is configured to receive source code and translate the source code to a low-level language. The source code is restricted to a subset of a high-level language and the low-level language is a specialized instruction set. Each statement of the subset of the high-level language directly maps to an instruction of the low-level language.

Abstract: An integrated circuit containing PMOS transistors may be formed by forming a dual layer hard mask. A first layer of the hard mask is halogen-containing silicon nitride formed using a halogenated silane reagent. A second layer of the hard mask is silicon nitride formed on the first layer using halogen-free reagents. After source/drain cavities are etched in the PMOS transistors, a pre-epitaxial bake with hydrogen is performed. After SiGe epitaxial source/drain regions are formed, the hard mask is removed.

Abstract: A method for forming MOS transistor includes providing a substrate including a semiconductor surface having a gate electrode on a gate dielectric thereon, dielectric spacers on sidewalls of the gate electrode, a source and drain in the semiconductor surface on opposing sides of the gate electrode, and a pre-metal dielectric (PAD) layer over the gate electrode and over the source and drain regions. Contact holes are formed through the PMD layer to form a contact to the gate electrode and contacts to the source and drain. A post contact etch dielectric layer is then deposited on the contacts to source and drain and on sidewalls of the PMD layer. The post contact etch dielectric layer is selectively removed from the contacts to leave a dielectric liner on sidewalls of the PMD layer. A metal silicide layer is formed on the contacts to the source and drain.

Abstract: One embodiment includes a power regulator system. The system includes a gate driver circuit configured to generate switching signal and a switching circuit package configured to receive the switching signal at a gate terminal. A signal return associated with the switching signal is provided at a gate return terminal. The switching circuit package also includes a switch that is periodically activated in response to the switching signal to generate a switching voltage at a switching node terminal. A filter stage includes an inductor interconnecting the switching node terminal and a node. The inductor can be configured to conduct a current in response to the switching voltage to generate an output voltage. A current sense circuit interconnects the gate return terminal and the node and measures a magnitude of the output current.

Abstract: An electronic device includes a first circuit (111) operable to generate at least a first and a second channel quality indicator (CQI) vector associated with a plurality of subbands for each of at least first and second spatial codewords respectively and generate a first and a second reference CQI for the first and second spatial codewords, and operable to generate a first and a second differential subbands CQI vector for each spatial codeword and generate a differential between the second reference CQI and the first reference CQI, and further operable to form a CQI report derived from the first and the second differential subbands CQI vector for each spatial codeword as well as the differential between the second reference CQI and the first reference CQI; and a second circuit (113) operable to initiate transmission of a signal communicating the CQI report. Other electronic devices, processes and systems are also disclosed.

Abstract: Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.

Abstract: Several circuits and methods for input offset control are disclosed. In an embodiment, a input offset control circuit includes a first input circuit and a second input circuit. The first input circuit is configured to operate within first common mode voltage range, configured to provide first input current, and configured to vary the first input current upon or subsequent to a variation of a voltage level in the first common mode voltage range. The second input circuit is coupled to the first input circuit and is configured to operate within second common mode voltage range, configured to provide a second input current, and configured to vary the second input current based on variation of the voltage level in the second common mode voltage range. Upon or subsequent to increasing the common mode voltage, the first input current is reduced and the second input current is increased.

Abstract: A processor includes an instruction fetch unit and an instruction decode unit. The instruction fetch unit includes an instruction pre-fetch buffer and is configured to fetch instructions from memory into the instruction pre-fetch buffer. The instruction decode unit is coupled to the instruction pre-fetch buffer and upon decoding a call instruction from the instruction pre-fetch buffer, causes next N instruction words of the instruction pre-fetch buffer to be preserved for execution after completing execution of a software module indicated by the call instruction, and causes the instruction fetch unit to begin fetching instructions of the software module from the memory at an address indicated by the call instruction. Upon completion of execution of the software module, the instruction decode unit begins to decode the preserved N instruction words while the instruction fetch unit concurrently fetches instruction words from beginning at an address after the N instruction words.

Abstract: Systems and methods for improved access point discoverability in multi-role multi-channel devices are described. When the multi-role multi-channel device leaves an AP role and then later returns to the AP role, such as when operating in another role, the multi-role multi-channel device sends a unicast probe response to the stations in a predetermined list. The unicast probe response is transmitted even without receiving a corresponding probe request. If one of the stations on the list is in the area and would like to connect to the AP role, it can complete the connection process using information in the response message.

Abstract: Integrated circuit apparatus and processes are presented for controlling a plurality of parallel-connected DC-DC converter phases forming a multiphase DC-DC conversion system in which individual converter phases are successively activated or deactivated for increasing and decreasing load conditions, respectively, according to an ordered phase sequence, and the phase sequence is selectively modified to promote thermal balancing of the DC-DC converter phases.

Abstract: One embodiment includes a power system. The system includes a power switch device that is activated to provide an output voltage to a load in response to an input voltage. The power switch device includes a control terminal and a bulk connection. The system also includes a reverse voltage control circuit configured to passively couple the input voltage to one of the control terminal and the bulk connection in response to a reverse voltage condition in which an amplitude of the input voltage becomes negative. The system further includes an output shutoff circuit configured to passively couple the output voltage to a neutral-voltage rail during the reverse voltage condition.