Abstract: A communications device configured to extract weighting factors from incoming signals received from two or more antennas while estimating a channel ratio for the signals. The device includes at least one antenna and a digital signal processor. The method includes receiving two signals and extracting the weighting factors while estimating the channel ratio.
Abstract: A method for determining a minimization factor for improving linearity of an analog-to-digital converter including a plurality of components includes the steps of: (a) Evaluating integral non-linearity response of the apparatus to identify significant departures of the response greater than a predetermined amplitude and to relate each respective significant departure with a respective identified component. (b) Determining magnitude of each significant departure. (c) Identifying a trimming factor related with each component. (d) Determining a residual gap magnitude for each significant departure. The residual gap magnitude comprises the magnitude of the respective significant departure less the trimming factor related with the identified component. (e) Determining the minimization factor as a sum of the residual gap magnitudes for a selected plurality of the identified components.
Abstract: A novel testing mechanism operative to test large capacitor arrays such as those used in a digitally controlled crystal oscillator (DCXO). The invention is adapted for use in DCXO circuits that employ dynamic element matching in their array decoding circuits. The invention combines the use of DEM during regular operation of the DCXO with a testing technique that greatly reduces the number of tests required. The invention tests the capacitors in the array on a row by row, wherein all the capacitors in a row are tested lumped together and treated as a single entity, which results in significantly reduced testing time. This permits the measurement of significantly higher frequency deviations due to the larger capacitances associated with an entire row of capacitors being tested.
Type:
Grant
Filed:
October 19, 2006
Date of Patent:
August 12, 2008
Assignee:
Texas Instruments Incorporated
Inventors:
John Wallberg, Robert B. Staszewski, Vanessa M. Bodrero
Abstract: Preprocessing for motion-compensated video encoding such as MPEG includes lowpass filtering, temporal (310) and/or spatial (312), locally per pixel in response to motion vector analysis and prediction error (304) and temporal change (306). This de-emphasizes image areas of rapid change which corresponds to human perception de-emphasis.
Abstract: Transcoding as from MPEG-2 SDTV to MPEG-4 CIF reuses motion vectors and downsamples in the frequency (DCT) domain with differing treatments of frame-DCT and field-DCT blocks, and alternatively uses de-interlacing IDCT with respect to the row dimension plus deferred column downsampling for reference frame blocks.
Abstract: A spatial light modulator comprises an array of micromirror devices each of which has a reflective and deflectable mirror plates. The mirror plates are moved between an ON and OFF state during operation, wherein the OFF state is a state wherein the mirror plate is not parallel to the substrate on which the mirror plate is formed. The micromirror device may have an ON state stopper for limiting the rotation of the mirror plate at the ON state angle, but does not have an OFF state stopper. The non-zero OFF state is achieved by attaching the mirror plate to a deformable hinge held by a hinge support that is curved at the natural resting state.
Abstract: A technique of improving antialiasing and adjacent channel interference filtering uses cascaded passive IIR filter stages combined with direct sampling and mixing. The methodology and related architecture allows for increased passive IIR filtering without necessitating use of amplifier stages.
Type:
Grant
Filed:
November 13, 2003
Date of Patent:
August 12, 2008
Assignee:
Texas Instruments Incorporated
Inventors:
Khurram Muhammad, Robert B. Staszewski, Dirk Leipold
Abstract: An optical projection and capture system includes an image sensor integrated with an optical projection device. Additionally, the integrated device may be coupled with a laser pointer to deliver interactive presentations. The laser pointer may be pulsed to improve identifying and tracking a laser light spot on a projected image. These applications may be extended to rear projection systems for gaming and interactive graphics.
Abstract: An apparatus comprising an insulating substrate having first and second surfaces and a plurality of metal-filled vias extending from the first to the second surface. The first and second surfaces have contact pads, each one comprising a connector stack to at least one of the vias. The stack comprises a seed metal layer in contact with the via metal capable of providing an adhesive and conductive layer for electroplating on its surface, a first electroplated support layer secured to the seed metal layer, a second electroplated support layer, and at least one reflow metal bonding layer on the second support layer. The electrolytic plating process produces support layers substantially pure (at least 99.0%), free of unwanted additives such as phosphorus or boron, and exhibiting closely controlled grain sizes. Reflow metal connectors provide attachment to chip contact pads and external parts.
Abstract: In accordance with a particular embodiment of the present invention, a method for manufacturing strained silicon is provided. In one embodiment, the method for manufacturing strained silicon includes inducing a curvature in a silicon wafer, depositing an epitaxial layer of silicon upon an upper surface of the silicon water while the silicon wafer is under the induced curvature, and releasing the silicon wafer from the induced curvature, after depositing the epitaxial layer, such that a strain is induced in the epitaxial layer.
Abstract: Various antenna designs that are small and cost effective are disclosed. In one design, the antenna is a bent and folded monopole antenna. In another design, the antenna is a folded and tapped monopole antenna. In yet another design, the antenna is a folded, bent, and tapped monopole antenna. The antennas may be part of a system using two back-to-back symmetric antennas. The antennas may be part of a modem, such as a wireless computer modem or a wireless handset.
Abstract: System and method for efficiently detecting packet format from a control channel. A preferred embodiment comprises the use of a slot counter (for example, slot counter 1310) to count the number of slots received (perhaps at a buffer, such as buffer 1305) since the last successfully demodulated packet. Using the slot counter, the number of demodulation attempts can be reduced. For example, if slot counter is one, then a single slot format decode is attempted. If slot counter is two, then a single and dual slot format decode is attempted. Additionally, channel quality can be used to determine likely channel formats. Furthermore, when multiple control channels are used, decoding information regarding one control channel can assist in determining the slot format of another.
Abstract: A method (10) of forming fully-depleted silicon-on-insulator (FD-SOI) transistors (150) and bulk transistors (152) on a semiconductor substrate (104) as part of an integrated circuit fabrication process is disclosed.
Abstract: In digital radio technology, information channels describing the properties of the associated performance channel(s) are included in the broadcast band. The digital radio determines when selected signal groups are present in the information channels. Upon identification of a selected signal group, the digital radio automatically reconfigures itself into a user-determined configuration for processing the performance channel. By way of specific example, the user can determine that the equalization of the performance channel for selected musical formats and/or selected artists.
Abstract: Various systems and methods for signal amplification are disclosed. For example, some embodiments of the present invention provide differential amplifiers that include dual transconductance characteristics. Such amplifiers include two dual input operational amplifiers that each include two input sets. A first of the input sets exhibits a first transconductance and a second of the input sets exhibits a second transconductance. The two dual input operational amplifiers are configured such that to a common mode signal, the amplifier exhibits an overall transconductance that is the difference between the first transconductance and the second transconductance. In contrast, to a differential signal, the overall transconductance is the sum of the first transconductance and the second transconductance.
Abstract: A system and are described as to adjusting voltages in a memory device, while the device is in sleep mode, to prevent or minimize voltage or current leakage of the device.
Abstract: Errors in an analog to digital converter that cause generated digital codes to deviate from expected values are corrected. A sample of an analog signal is stored in a storage element. An error signal is then generated, with the error signal representing a deviation of an expected digital code for the strength of a sample of an analog input from a value that would be generated without correction. The error signal is then added to the stored sample. In an embodiment implemented in the context of a SAR ADC, a digital value representing an integral non-linearity error is generated based on a partial digital code (result of a partial conversion of the sample) and an error coefficient. The digital value is converted to analog form by an auxiliary DAC, and added to the stored input sample.
Abstract: A shielded electronic package, comprising a semiconductor device, an insulating housing surrounding the semiconductor device and a metal coating on the insulating housing. The metal coating covers all but those portions of the insulating housing that are adjacent to connective structures on one or more mounting sides of the insulating housing.
Abstract: A method of verifying consistency between a circuit schematic and a corresponding integrated circuit layout is disclosed. The method includes identifying a voltage condition associated with a portion of the circuit schematic, and assigning a pseudo diode to the portion of the circuit schematic that is uniquely associated with the identified voltage condition. The method further includes coding a pseudo layer associated with an integrated circuit layout of the circuit schematic in accordance with content of the assigned pseudo diode, and verifying consistency between the circuit schematic and the corresponding integrated circuit layout by extracting the pseudo layer from the integrated circuit layout and comparing information of the pseudo layer to the assigned pseudo diode in the circuit schematic.
Type:
Application
Filed:
December 21, 2007
Publication date:
August 7, 2008
Applicant:
Texas Instruments Incorporated
Inventors:
Wen-Hwa M. Chu, Shaibal Barua, Lily X. Springer, James Homack
Abstract: A system interface having an interface for dual battery packs provides for power up sequencing of battery packs and pack switching under the control of a host processor within associated system electronics. The host processor communicates with each battery pack via a pack interface that includes a single wire mode control signal and a single wire status signal. The mode control signal allows the host processor to control the operational mode of selector switches within the respective battery pack. The single wire status signal provides status information to the host processor regarding the state of the selector switches within the respective battery pack. The mode and status signals are multi-state signals that permit at least three states to be identified via the single wire interface. Selector switches are provided only in the battery packs. No selector switches are included in the system electronics to minimize voltage drops between the selected battery pack and the system electronics.
Type:
Grant
Filed:
April 8, 2005
Date of Patent:
August 5, 2008
Assignee:
Texas Instruments Incorporated
Inventors:
Jose Antonio Vieira Formenti, Garry Ross Elder