Abstract: This invention is codebook sub-sampling of the reporting of RI, CQI, W1 and W2. If CSI mode 1 is selected RI and W1 are jointly encoded using codebook sub-sampling in report 1. If CSI mode 2 is selected W1 and W2 are jointly encoded using codebook sub-sampling in report 2.

Abstract: An integrated circuit is formed by removing a sacrificial gate dielectric layer and a sacrificial gate to form a gate cavity. A conformal dielectric first liner is formed in the gate cavity and a conformal second liner is formed on the first liner. A first etch removes the second liner from the bottom of the gate cavity, leaving material of the second liner on sidewalls of the gate cavity. A second etch removes the first liner from the bottom of the gate cavity exposed by the second liner, leaving material of the first liner on the bottom of the gate cavity under the second liner on the sidewalls of the gate cavity. A third etch removes the second liner from the gate cavity, leaving an L-shaped spacers of the first liner in the gate cavity. A permanent gate dielectric layer and replacement gate are formed in the gate cavity.

Abstract: Resonant impedance sensing with a resonant sensor (such as LC) is based on generating a controlled negative impedance to maintain steady-state oscillation in response to changes in resonance state caused by interaction with a target. Resonant impedance sensing can include: (a) generating a controlled negative impedance at the sensor; (b) controlling the negative impedance based on a detected resonance state to substantially cancel the sensor resonant impedance, such that the sensor resonance state corresponds to steady-state oscillation, where the negative impedance is controlled by a negative impedance control loop that includes the sensor resonator as a loop filter; and (c) providing sensor response data based on the controlled negative impedance, such that the sensor response data represents a response of the sensor to the target. Thus, the response of the sensor to the target corresponds to the negative impedance required for steady-state oscillation.

Abstract: One embodiment includes a power system. The system includes a power switch device that is activated to provide an output voltage to a load in response to an input voltage. The power switch device includes a control terminal and a bulk connection. The system also includes a reverse voltage control circuit configured to passively couple the input voltage to one of the control terminal and the bulk connection in response to a reverse voltage condition in which an amplitude of the input voltage becomes negative. The system further includes an output shutoff circuit configured to passively couple the output voltage to a neutral-voltage rail during the reverse voltage condition.

Abstract: A clam shell wafer holder includes a base and a lid pivotally connected with the base by an integral hinge. The base includes a rotatable wafer support, and the lid includes a universal frame and a pin holder attachment spaced inwardly from the frame. Only two contact pins are formed in a wafer-facing surface of the pin holder attachment. The contact pins are manually aligned with and contact two points on a wafer when the lid is closed against the base. A method for holding a wafer for plating is provided using the disclosed holder apparatus.

Abstract: A master electronic circuit includes a storage representing a wireless collision avoidance networking process involving collision avoidance overhead and combined with a schedulable process including a serial data transfer process and a scheduler, a wireless modem operable to transmit and receive wireless signals for the networking process and a processor coupled with the storage and with the wireless modem and operable to execute the scheduler to establish and transmit a schedule for plural serial data transfers involving the processor and distinct station identifications, and to execute the serial data transfers inside the wireless networking process and according to the schedule so as to avoid at least some of the collision avoidance overhead. Other electronic circuits, processes of making and using, and systems are disclosed.

Abstract: In an embodiment of the invention, a dual-port positive level sensitive data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal (CKT) goes high, (CLKZ) goes low and retention control signal is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit (D2), the clock signals (CKT) and (CLKN), the retain control signals (RET) and the control signals SS (SS) and (SSN). The signals (CKT), (CLKZ), (RET), (SS) and (SSN) determine whether the output of the clocked inverter or the second data bit (D2) is latched in the dual-port latch. Control signal (RET) determines when data is stored in the dual-port latch during retention mode.

Abstract: Within an electronic device, a voltage regulator powers a load. The voltage regulator has adjustable operating parameters that can be set during operation of the electronic device. The adjustable operating parameters are set or reset in accordance with a state of the electronic device, or a portion thereof having the load, in order to optimize power usage. The state is selectable from at least three predetermined states. Values for the operating parameters are selectable from a plurality of sets of values. Each set of values corresponds to at least one of the predetermined states.

Abstract: Integrated circuits and methods for testing integrated circuits are disclosed herein. An embodiment of an integrated circuit includes a microprocessor and memory that is accessible by the microprocessor. The integrated circuit also includes reconfigurable logic, wherein a first test program for testing at least one of the microprocessor and memory is loadable onto the reconfigurable logic. At least one other program is loadable into the reconfigurable logic after the first test program runs.

Abstract: This invention is a technique for coordinate multi-point wireless transmission between plural base stations and user equipment. At least one base station transmits via a Physical Downlink Shared CHannel (PDSCH). The user equipment does not know the identity of the plural base stations. This could include joint transmission by simultaneous data transmission from multiple base stations. This could include dynamic point selection by data transmission from one base station at a time and changing the transmitting point (TP) from one subframe to another subframe. This could include coordinated scheduling/beamforming (CS/CB) where data is transmitted to the user equipment from one base station at a time and the base stations communicate to coordinate user scheduling and beamforming. The transmission point (TP) could vary over Resource Block (RB) pairs within a subframe while never transmitting from more than one base station. The transmission point (TP) could change in a semi-static fashion.

Abstract: A method and apparatus for active noise canceling. The method includes retrieving an input sample from at least one of a feedback or feedforward microphone digitized through the sigma-delta converter, retrieving the input sample and a related filter, wherein the filter is customized to the particular headset, outputting a filtered signal through a speaker without any interpolation and reducing order of CIC filters, and outputting a response sharply tapered down.

Abstract: A method of detecting lost data within a data stream by inserting sequence numbers within the stream. Network data blocks to be transmitted are assembled from data chunks, where each data chunk contains a sequence number. Where the data is originating from multiple sources, the sequence numbers are labeled with an unique source ID, and are inserted into the composite data stream after one or more data chunks are generated.

Abstract: The disclosure describes a novel method and apparatus for allowing response data output from the scan outputs of a circuit under test to be formatted and applied as stimulus data input to the scan inputs of the circuit under test. Also the disclosure described a novel method and apparatus for allowing the response data output from the scan outputs of a circuit under test to be formatted and used as expected data to compare against the response data output from the circuit under test. Additional embodiments are also provided and described in the disclosure.

Abstract: A method for acoustic echo cancellation in a communication device is provided that includes receiving a first near-end audio signal in the communication device, wherein the first near-end audio signal comprises acoustic echo of a far-end audio signal reproduced by the communication device, and performing echo cancellation on the first near-end audio signal to generate a second near-end audio signal with at least some of the acoustic echo removed, wherein the echo cancellation is performed responsive to presence or absence of double-talk (DT), and wherein a zero-crossing rate (ZCR) is used to detect the presence or absence of DT.

Abstract: A method of encoding a digital video sequence is provided that includes computing a motion vector (MV) histogram and a motion threshold for a first frame of the digital video sequence, and using the MV histogram and the motion threshold for one selected from a group consisting of adaptive fcode determination and adaptive coding structure determination.

Abstract: An integrated circuit die includes a substrate of semiconductor material having a top surface, a bottom surface, and an opening through the substrate between the top surface and the bottom surface. A through silicon via (TSV) has a conductive body in the opening, has a top contact point coupled to the body at the top surface, and has a bottom contact point coupled to the body at the bottom surface. A scan cell has a serial input, a serial output, control inputs, a voltage reference input, a response input coupled to one of the contact points, and a stimulus output coupled to the other one of the contact points.

Abstract: The problem of high test cost of manufactured goods can be partially solved by lowering the percentage of the goods to be tested methodically while keeping the total defective portion of the goods expressed in DPPM below a preset target value. The method includes identifying a first test that is capable of screening out enough parts that would fail a second test so that the portion of the parts to be tested second test can be reduced. The number of parts screened out by the first test determines if the reduced testing scheme would violate the preset DPPM target value.

Abstract: A device includes multiple transceivers, a coupling block and an antenna. The transceivers operate according to time-division multiple access (TDMA) techniques. The coupling block is designed to enable the multiple transceivers to transmit or receive corresponding signals using the antenna. The multiple transceivers include a first transmitter and a second transmitter. The first transmitter is connected to the antenna via a first coupling network. The second transmitter is connected to the antenna via a series connection of a second coupling network and at least a portion of the first coupling network. Other transmitters are connected to the antenna via a series arrangement of at least a portion of the first coupling network and corresponding coupling networks.

Abstract: A semiconductor device contains a photodiode formed in a substrate of the semiconductor device. At a top surface of the substrate, over the photodiode, a surface grating of periodic field oxide in a periodic configuration and/or gate structures in a periodic configuration is formed. The field oxide may be formed using an STI process or a LOCOS process. A semiconductor device with a surface grating including both field oxide and gate structures has the gate structures over the semiconductor substrate, between the field oxide. The surface grating has a pitch length up to 3 microns. The surface grating covers at least half of the photodiode.

Abstract: A device for updating complex channel gain estimates for orthogonal frequency division multiplexed (OFDM) symbols that includes a receiver to receive a plurality of OFDM symbols, wherein each OFDM symbol includes a plurality of pilot tones at a subset of odd positions and a finite impulse response (FIR) filter. The FIR filter configured to filter a plurality of initial channel estimates of odd tones of an OFDM symbol using a first set of coefficients to generate an updated estimate of the channel estimates of the plurality of odd tones for that OFDM symbol, and filter the plurality of the initial channel estimates of the odd tones of the OFDM symbol using a second set of coefficients to generate estimates for a plurality of initial channel estimates of even tones for that OFDM symbol.