Patents Assigned to Texas Instruments
  • Patent number: 7408369
    Abstract: Systems and methods are disclosed to enable determining thermal protection characteristics of an integrated circuit. In one embodiment, an integrated circuit includes a proportional to absolute temperature (PTAT) generator that provides a PTAT signal that varies as a function of temperature. Thermal protection control system provides an output signal indicative of a thermal protection condition based at least in part on the PTAT signal. A monitoring system that provides a path to enable selective measuring of at least one signal associated with operation of the thermal protection control system.
    Type: Grant
    Filed: May 5, 2005
    Date of Patent: August 5, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Kenneth George MacLean, David John Baldwin, David Alexander Grant
  • Patent number: 7407291
    Abstract: The micromirror-based projection system of the present invention uses polarized illumination light in producing desired images on a display target. The display target has coated thereon a polarization film that absorbs most of the ambient light that would be incident onto the display target otherwise. Polarized illumination light is provided incident to the reflective surfaces of the spatial light modulator. The polarization direction of the illumination light can be associated with the rotation axes of the micromirrors and the polarization direction of the polarized film on the display target.
    Type: Grant
    Filed: June 3, 2005
    Date of Patent: August 5, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Regis Grasser, Andrew Huibers
  • Patent number: 7407850
    Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that employ high-k dielectric layers. An n-type well region (304) is formed within a semiconductor body (302). A threshold voltage adjustment implant is performed by implanting a p-type dopant into the n-type well region to form a counter doped region (307). A high-k dielectric layer (308) is formed over the device (300). A polysilicon layer (310) is formed on the high-k dielectric layer and doped n-type. The high-k dielectric layer (308) and the polysilicon layer (310) are patterned to form polysilicon gate structures. P-type source/drain regions (306) are formed within the n-type well region (304).
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: August 5, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Ramesh Venugopal, Christoph Wasshuber, David Barry Scott
  • Patent number: 7408980
    Abstract: A semi-distributed method of managing the spectral power over multiple digital subscriber line communication loops (LP1, LP2) is disclosed. A central office (CO) DSL transceiver (10) and a remote terminal (RT) DSL transceiver (15) communicate with customer premises equipment (CPE) (121, 122) over separate twisted-pair wire loops (LP1, LP2) that are in sufficient physical proximity with one another as to suffer from crosstalk. A network management center (NMC) (20) initializes a price parameter, which is used by the CO (10) and RT (15) in independent maximization problems. The CO (10) derives a maximum tolerable power spectral density for the RT (15) that permits the CO (10) to reach a target data rate, and the RT (15) derives an actual power spectral density that maximizes its data rate, each using the price parameter. The NMC (20) compares the actual RT power spectral density to the tolerable RT power spectral density, and adjusts the price parameter accordingly, with the process repeating until convergence.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: August 5, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: Georgios Ginis
  • Patent number: 7408392
    Abstract: A converter circuit and method for converting a pulse-width modulated input signal into a voltage output signal eliminates an offset due to component mismatch. The converter circuit includes at least two channels. Each channel has an operational amplifier with differential inputs and differential outputs. A first capacitor in each channel provides a negative feedback from a first output to a first input and a second capacitor in each channel provides a negative feedback from a second output to a second input. Each channel is conditioned by a switch array in response to the pulse-width modulated signal to operate in a selected one of an integration mode, a sampling mode and a reset mode. In each channel, in the integration mode, the switch array selectively connects the reference current source of first polarity either to the first or to the second input of the operational amplifier, and the reference current source of second polarity to the other of the first and second inputs.
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: August 5, 2008
    Assignee: Texas Instruments Deutschland GmbH
    Inventor: Mikhail Ivanov
  • Patent number: 7408485
    Abstract: A sample rate converter suitable for use in an audio DAC includes a first estimating circuit (32A) generating first (TR) and second (STAMPR) signals synchronized to an asynchronous clock (MCLK) and representing the period and edge arrival times, respectively, of a reference clock (REFCLK). A second estimating circuit (32B) operates on the first and second signals to generate third (T1) and fourth (STAMP1) signals representing an input sample rate (32fsin) and arrival times of input data samples, respectively, which are applied to a coefficient and address generator (76) to generate read addresses and coefficients input to a FIFO memory (42) receiving digital input data at the input sample rate and a multiplication/accumulation circuit (78) receiving data from the FIFO memory. The multiplication/accumulation circuit produces an output signal (SRC-out) synchronized to the asynchronous clock at an output sample rate (32fsout).
    Type: Grant
    Filed: March 22, 2007
    Date of Patent: August 5, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Shawn Xianggang Yu, Terry L. Sculley
  • Patent number: 7408415
    Abstract: A phase locked loop circuit comprises a voltage controlled oscillator with a control input to which a variable control voltage is applied and a phase-frequency discriminator with an output connected to a loop filter to produce the control voltage. To provide the phase locked loop circuit with a low loop gain and a wide frequency pulling range, a plurality of discrete capacitors is associated with the voltage controlled oscillator. A switch array selectively activates and deactivates each of the capacitors in the voltage controlled oscillator. Each number of currently activated capacitors determines one out of a plurality of partial ranges of frequencies through which the oscillator can be tuned by a variation of the control voltage in a range between predetermined upper and lower control voltage limits. A total frequency range through which the oscillator can be tuned is divided thus into a plurality of partial frequency ranges each defined by a different number of activated capacitors.
    Type: Grant
    Filed: November 28, 2005
    Date of Patent: August 5, 2008
    Assignee: Texas Instruments Deutschland GmbH
    Inventors: Markus Dielt, Elmar Werkmeister
  • Patent number: 7409415
    Abstract: An electronic system (2001) for manipulating an input data argument (D[31:0]) comprising an integer number of bits. The system comprises an input (R) for receiving a right direction argument and an input (L) for receiving a left direction argument. The system also comprises circuitry (200) for producing a first data output having the integer number of bits by rotating the input data argument in response to the first direction argument and the second direction argument. The system also comprises circuitry for providing a modified data output (502). The circuitry for providing comprises circuitry for selecting a first set of bits from the first data output as a first portion of the modified data output and circuitry for providing a second set of bits from a source other than the first data output as a second portion of the modified data output.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: August 5, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: Patrick W. Bosshart
  • Patent number: 7408250
    Abstract: A microstructure is packaged with a device substrate of the microstructure being attached to a package substrate. For dissipating possible deformation of the microstructure, which may result in device failure or quality degradation of the microstructure, an adhesive material comprising a compliant adhesive component is applied and positioned between the device substrate and package substrate.
    Type: Grant
    Filed: April 5, 2005
    Date of Patent: August 5, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Jonathan Doan, Terry Tarn
  • Patent number: 7409611
    Abstract: In a first embodiment a TAP 318 of IEEE standard 1149.1 is allowed to commandeer control from a WSP 202 of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface.
    Type: Grant
    Filed: June 21, 2004
    Date of Patent: August 5, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 7408493
    Abstract: Systems and methods for automatic gain control are disclosed. In one aspect of the invention, a system is provided that comprises a programmable gain amplifier that amplifies an input signal based on a gain signal. The system further comprises an analog-to-digital converter that generates at least one digital output signal from the amplified input signal, and an automatic gain control component that determines an adjustment of the gain signal based on a comparison of the at least one digital output signal to a predetermined maximum amplitude reference level.
    Type: Grant
    Filed: May 20, 2005
    Date of Patent: August 5, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Itay Lusky, Ofir Shalvi, Liran Brecher
  • Publication number: 20080180299
    Abstract: A new analog-to-digital (ADC) circuit and architecture and the corresponding method of implementation are provided. The analog input signal is converted into a modulated pulse stream such as by a pulse-width-modulation scheme. The time-duration width of the pulses are measured by a TDC (time-to-digital converter) and converted to a digital binary representation that is directly correlated with the voltage amplitude of the analog input signal. The circuit implementation is substantially free of switches and circuit issues such as associated with sigma-delta and switched-capacitor techniques for ADC's.
    Type: Application
    Filed: January 26, 2007
    Publication date: July 31, 2008
    Applicant: Texas Instruments Incorporated
    Inventor: Brett Forejt
  • Publication number: 20080183931
    Abstract: A method or device handles memory management faults in a device having a digital signal processor (“DSP”) and a microprocessor. The DSP includes a memory management unit (“DSP MMU”) to manage memory access by the DSP, and the DSP and the microprocessor access shared physical memory. Upon the DSP executing an instruction attempting to access a virtual address wherein the virtual address is invalid, a page fault interrupt is generated by the DSP MMU. A microprocessor interrupt handler in the microprocessor is activated in direct response to the page fault interrupt. Thereafter in the microprocessor, a translation lookaside buffer (“TLB”) entry is created in the DSP MMU, which includes a valid mapping between the virtual address and a page of physical memory. After creating the TLB entry, the microprocessor indicates to the DSP that the access by the DSP of the virtual address is completed.
    Type: Application
    Filed: January 30, 2007
    Publication date: July 31, 2008
    Applicant: Texas Instruments Incorporated
    Inventors: Atul Verm, Samant Kumar
  • Publication number: 20080181038
    Abstract: A method and system are described for a two step precharging of bitlines in a memory array. In the first step a partial precharge of the bitline is accomplished with a lower power supply, the second step completes the bitline precharge with the higher power supply. Since the higher power supply must ultimately supply the final bitline precharge voltage achieving a partial bitline precharge with a lower power supply will result in lower sram and system power.
    Type: Application
    Filed: December 27, 2007
    Publication date: July 31, 2008
    Applicant: Texas Instruments
    Inventor: Michael Patrick Clinton
  • Publication number: 20080181033
    Abstract: A system and are described as to adjusting voltages in a memory device, while the device is in sleep mode, to prevent or minimize voltage or current leakage of the device.
    Type: Application
    Filed: December 27, 2007
    Publication date: July 31, 2008
    Applicant: Texas Instruments
    Inventor: Michael Patrick Clinton
  • Patent number: 7406494
    Abstract: An efficient method of generating a bit-reverse index array in real time without performing any bit manipulation for a wireless communication system.
    Type: Grant
    Filed: May 14, 2003
    Date of Patent: July 29, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: David P. Magee
  • Patent number: 7406178
    Abstract: The present invention is a digital dynamic compression or automatic gain control (AGC) (10) adapted for use in high quality audio and hearing aids applications. An efficient digital AGC design employs two compact ROM-based tables (ROM_CSD, ROM_SPL) in addition to two comparators (COMP_A, COMP_B) and several registers (REG_A, REG_B, ADDR_A, ADDR_B). While one ROM stores the values of discrete input signal levels, the other contains gain codes based on a canonical signed digit (CSD) coding approach that leads to a very simple gain multiplier (20). In many cases an extremely compact table for gain values can be achieved by reusing a single small-size ROM that behaves like one that is several time larger. Two design examples are shown to expound the insights of the new digital AGC design. For the less-than-half-dB-gain-step cases only two adders are required for the multiplier whereas just three adders are needed in the situations with less than quarter-dB gain steps.
    Type: Grant
    Filed: April 6, 2001
    Date of Patent: July 29, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Zhongnong Jiang, James R. Hochschild
  • Patent number: 7405685
    Abstract: A novel method and apparatus for a negative contributive offset compensation mechanism for a transmit buffer adapted to compensate for the positive offset generated by higher order sigma-delta modulators used to amplitude modulate the transmit buffer. The positive outputs from the sigma-delta modulator are processed differently than the negative outputs. The inverters associated with the negative outputs in the sigma-delta modulator are removed and the clock signal used to drive the transistors corresponding to the negative outputs is negated or shifted 180 degrees from the clock used to drive the transistors corresponding to the positive outputs. A non-inverted version of the clock is used with the positive outputs and an inverse clock is used with the negative outputs. Use of the inverse clock causes a negative contributive offset to be generated that is added on the second half cycle of each clock. The result is an offset compensated RF output signal having zero offset.
    Type: Grant
    Filed: July 11, 2005
    Date of Patent: July 29, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Sameh S. Rezeq, Dirk Leipold, Robert B. Staszewski, Chih-Ming Hung
  • Patent number: 7405856
    Abstract: A display system includes a light source 110 and a spatial light modulator 122 located to receive light from the light source. The spatial light modulator (e.g., a DMD) includes a number of independently controllable elements that are activated for a period of time to display light of a desired brightness. A light sensor 136 is located to determine a characteristic of light from the light source 110. A control circuit 126 is coupled to the spatial light modulator 122 and controls the period of time that the independently controllable elements are activated. This period of time is based at least in part by an input received from the light sensor 136.
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: July 29, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Donald B. Doherty, Daniel J. Morgan
  • Patent number: 7404513
    Abstract: A semiconductor device with a chip having at least one metallic bond pad (101) over weak insulating material (102). In contact with this bond pad is a flattened metal ball (104) made of at least 99.999% pure metal such as gold, copper, or silver. The diameter (104a) of the flattened ball is less than or equal to the diameter (103a) of the bond pad. A wire (110) is connected to the bond pad so that the wire has a thickened portion (111) conductively attached to the flattened metal ball. The wire is preferably made of composed metal such as gold alloy. The composition of the flattened ball is softer than the wire. This softness of the flattened ball protects the underlying insulator against damage caused by pressure or stress, when the composed ball is attached.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: July 29, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Sohichi Kadoguchi, Norihiro Kawakami