Abstract: A projection system, a spatial light modulator, and a method for forming a micromirror array such as for a projection display are disclosed. The spatial light modulator can have two substrates bonded together with one of the substrates comprising a micro-mirror array. The two substrates can be bonded at the wafer level after depositing a getter material and/or solid or liquid lubricant on one or both of the wafers if desired. In one embodiment of the invention, one of the substrates is a light transmissive substrate and a light absorbing layer is provided on the light transmissive substrate to selectively block light from passing through the substrate. The light absorbing layer can form a pattern, such as a frame around an array of micro-mirrors.

Abstract: A method of communicating data across a channel that experiences near-end cross talk (NEXT) interference and far-end cross talk (FEXT) interference in alternate intervals. In one embodiment, the method comprises: a) determining NF, the number of bits per symbol usable in a FEXT-only mode of operation; b) determining NS, a number of bits per symbol usable in a single mode of operation; c) determining whether the FEXT-only mode or the single mode provides a higher data rate; and d) configuring a modem to transmit using the mode having a higher data rate. The FEXT-only mode may be determined to have a higher data rate when 126NF>340NS.

Abstract: The invention provides a method for manufacturing a microelectronic device and a microelectronic device. The method for manufacturing the microelectronic device, without limitation, may include forming a first mirror layer over and within one or more openings in a sacrificial spacer layer, and forming a dielectric layer over an upper surface of the first mirror layer and within the one or more openings. The method may further include subjecting the dielectric layer to an etch, the etch removing the dielectric layer from the upper surface and leaving dielectric portions along sidewalls of the one or more openings, and forming a second mirror layer over the first mirror layer and within the one or more openings, the dielectric portions separating the first mirror layer and the second mirror layer along the sidewalls.

Abstract: In a method and system for fabricating a thermally enhanced semiconductor device (200, 300) is packaged as a through hole single inline package (SIP). A leadframe (210, 310, 410) having a die pad (220, 320, 420) to attach an IC die (230, 330), a first plurality of conductive leads (240, 340, 430) formed from a first portion of metal sheet (432), and a second portion of metal sheet (440) disposed on an opposite side of the IC die (230, 330) as the first plurality of conductive leads is stamped from a metal sheet. The first plurality of conductive leads (240, 340, 430) are arranged in a single line and are capable of being through hole mounted in accordance with the SIP. The second portion of metal sheet (440) includes the die pad (420) to form a heat spreader (260, 360) in the form of the metal sheet. The heat spreader (260, 360) provides heat dissipating for the heat generated by the IC die (230, 330).

Abstract: The present invention provides a thermostatic bias controller for use with a memory array. The thermostatic bias controller includes a temperature sensing circuit configured to sense a temperature associated with the memory array. The thermostatic bias controller also includes a voltage control circuit coupled to the temperature sensing circuit and configured to provide a bias voltage to at least one back-gate of the memory array based on the temperature.

Abstract: The present invention provides an FFT/IFFT processor for use with N data values. In one embodiment, the FFT/IFFT processor includes an even-odd data mapper configured to provide a mapping of the N data values into N/2 mapped complex data values if the N data values are real. Additionally, the FFT/IFFT processor also includes a separator-combiner, coupled to the even-odd data mapper, configured to compute either an FFT based on the mapping or an IFFT based on the N data values if the N data values are complex.

Abstract: Scan tests tolerant to indeterminate states generated in an integrated circuit (IC) when employing signature analysis to analyze test outputs. Bits with indeterminate-state are masked when scanning out the bits from the scan chains to force such indeterminate bits to a known logic level. This prevents a signature generator receiving the outputs of a scan test from generating an invalid signature. In an embodiment, masking information is stored in encoded form in a memory. A decoding circuit decodes the masking information and provides mask data under control from a mask controller. Mask data is sent to a masking circuit which also receives corresponding bits from scan-out vectors, with each scan-out vector being generated by a corresponding one of multiple scan chains. The output of the masking circuit may be provided in a compressed form to the signature generator circuit.

Abstract: Disclosed herein are methods for providing a load/reset sequence for a visual display system (100) having a phased reset spatial light modulator (SLM) (14). The SLM (14) has pixels (21) that are addressable with data by means of loads (ld) and resets (r), where the data is formatted in bit-planes (0-14)and each bit-plane is loaded as one or more segments (S0-S5) in a predetermined sequence during a frame-time. In one embodiment, the method comprises storing a display order of the segments (S0-S5) and determining whether resetting any of the segments (S0-S5) conflicts with the resetting of another of the segments (S0-S5), thereby identifying a conflicting segment.

Abstract: According to one embodiment of the present invention, a semiconductor device includes a first layer of dielectric material disposed upon an upper surface of a substrate of the semiconductor device, a first layer of metal disposed upon an upper surface of the first layer of dielectric material, and a thick film anti-reflective layer having a thickness of at least about one micron disposed upon an upper surface of the first layer of metal.

Abstract: A novel method of packaging electronic devices (e.g. any device that receives or transmits electronic signals) including microelectromechanical devices, semiconductor devices, light emitting devices, light modulating devices, light modulating devices, and light detecting device has been provided herein. The electronic device is placed between two substrates, at least one of which has a cavity for holding the electronic device. The two substrates are then bonded and hermetically sealed with a sealing medium. The adhesion of the sealing medium to the substrates, especially when one of the two substrates is ceramic, can be improved by applying a metallization layer to the surface of the substrate.

Abstract: A method and system providing boundary dispersion to pixel values displayed on a binary spatial light modulator to reduce temporal contouring artifacts. Pixel code values are offset from a nominal value when displayed on the SLM to disperse a large bit transition for a pulse width modulation (PWM) system. The offset value varies as a function of the pixel digital code, the pixel spatial location on the screen, and pixel temporal location in time. The set of offsets applied to pixels is varied over a repeating sequence of 2 displayed frames.

Abstract: The present invention provides the method includes forming source/drain regions 170 in a semiconductor wafer substrate 110 adjacent a gate structure 130 located on a front side of the semiconductor wafer substrate 110. The source/drain regions 170 have a channel region 175 located between them. A first stress-inducing layer 190 is placed on a backside of the semiconductor wafer substrate 110 and is subjected to a thermal anneal to cause a stress to form in the channel region 175.

Abstract: An unconnected power save method reduces the battery consumption of a wireless station in a wireless local area network (WLAN). A wireless station enters a sleep mode between scans for a prospective access point. The sleep duration time is determined using the current position of the station relative to the WLAN network topology.

Abstract: An integrated circuit thin film resistor structure includes a first dielectric layer (18A) disposed on a semiconductor layer (16), a first dummy fill layer (9A) disposed on the first dielectric layer (18B), a second dielectric layer (18C) disposed on the first dummy fill layer (9A), the second dielectric layer (18B) having a first planar surface (18-3), a first thin film resistor (2) disposed on the first planar surface (18-3) over the first dummy fill layer (9A). A first metal interconnect layer (22A,B) includes a first portion (22A) contacting a first head portion of the thin film resistor (2). A third dielectric layer (21) is disposed on the thin film resistor (2) and the first metal interconnect layer (22A,B). Preferably, the first thin film resistor (2) is symmetrically aligned with the first dummy fill layer (9A). In the described embodiments, the first dummy fill layer is composed of metal (integrated circuit metallization).

Abstract: Disclosed is a system and method for aligning a free-space optical signal in an optical system having a light modulator having an array of pixels. In this system and method, certain pixels of the light modulator array are initially assigned for the modulation of the free-space optical signal. An alignment optical signal is generated and monitored, to determine whether the optical system components are properly aligned. The alignment optical signal is generated and propagated along a path that is substantially aligned with the path of the free-space optical signal. Detector elements are used to monitor the position (and shifts in the position) of the free-space optical signal. By reassigning the pixels of the array of the light modulator at the direction of a control system, it is possible for the light modulator to compensate for shifts in the alignment of the optical components within the system.

Abstract: The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region, wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer, and subjecting the exposed nitridated, high voltage dielectric to a high vacuum to remove the accelerant residue.

Abstract: An improved window frame and window piece for a micromirror assembly is disclosed herein. The window frame includes a stress-relieving contour positioned in the middle of the frame that can absorb the mechanical stresses applied to the window frame from the ceramic base and from the window piece. The window frame may be comprised of a single piece of sheet metal that has been stamped to include a stress-relieving contour. The stress-relieving contour may be comprised of a variety of shapes, including a “U” shape, an inverted “U” shape, a curved step shape, or other combinations thereof.

Abstract: A sleep control system and method are provided that permit a reference clock and the direct sequence spread spectrum (DSSS) modem in a mobile station receiver to be turned off and turned back on at arbitrary points in time while still maintaining accurate base station system time. Accurate timing is made possible through a number of techniques including precise initial calibration using a rising edge/falling edge averaging system, determining the sleep clock and reference clock frequencies, and the determination of the frequency drift of the sleep clock that occurred during the previous sleep interval.

Abstract: A thin film resistor structure and a method of fabricating a thin film resistor structure is provided. The thin film resistor structure includes an electrical interface layer or head layer that is a combination of a Titanium (Ti) layer and a Titanium Nitride (TiN) layer. The combination of the Ti layer and the TiN layer mitigates resistance associated with the electrical interface layers.

Abstract: An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A dedicated scan cell has a functional data output separate from a test data output. Shared scan cells each have a combined output for functional data and test data. The shared scan cells are coupled in series. The test data input of the first shared scan cell is connected to the test data output of the dedicated scan cell. The combined output of one shared scan cell is coupled to the test data input lead of another shared scan cell. The multiplexer has an input coupled to the test data output, an input connected to the combined output lead of the last shared scan cell in the series, and an output connected in the scan path.