Abstract: In a first embodiment a TAP of IEEE standard 1149.1 is allowed to commandeer control from a WSP of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface. One approach provides for the TAP to maintain access and control of the TAP instruction register, but provides for a selected data register to be accessed and controlled by either the TAP+ATC or by the discrete CaptureDR, UpdateDR, TransferDR, ShiftDR, and ClockDR WSP data register control signals.

Abstract: The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus. According to the present disclosure, the TAP's TMS terminal is used as a clock signal and the TCK terminal is used as a bidirectional data signal to allow serial communication to occur between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC.

Abstract: According to one embodiment of the invention, a mold tool for packaging integrated circuits includes a first mold press die including a first non-planar surface and a second mold press die including a second non-planar surface. The first and second non-planar surfaces form the upper and lower surfaces of a mold cavity when the first and second mold press die are engaged. The mold tool also includes a bright TiN coating disposed on the first non-planar surface. The bright TiN coating operates to decrease residue on the first non-planar surface from a mold compound.

Abstract: A spatial light modulator has an array of reflective surfaces of deflectable mirror plates. For improving the reflectivity of the mirror plates, layers that are preferably transmissive to visible light are provided on the reflective surfaces of the mirror plates. The layers may have different thicknesses and/or refractive indices to the visible light to optimize the reflectivity of the mirror plates.

Abstract: According to one embodiment of the invention, a system used in auto-boating includes a tape substrate supported by a boat. The tape substrate includes a pair of lateral edges parallel to one another and each having respective first and second ends, and a pair of longitudinal guide strips parallel to one another. One of the longitudinal guide strips extends between the respective first ends of the pair of lateral edges and the other longitudinal guide strip extends between the respective second ends of the pair of lateral edges. The tape substrate also includes a plurality of die attach regions disposed within the area defined by the pair of lateral edges and the pair of longitudinal guide strips. The system further includes a boat clip coupled to the boat such that the tape substrate is sandwiched between the boat and the boat clip. Each longitudinal guide strip includes a pair of tabs disposed at opposite ends thereof such that each tab extends beyond a respective one of the lateral edges.

Abstract: A thermal inkjet printhead 100 of the present invention includes a heating element 110, an ink chamber, control circuitry 108, an ink reservoir, and a memory array 106. The control circuitry 108 causes the heating element to generate thermal energy thereby causing ink within the ink chamber to generate bubbles of ink, which are then expelled through a nozzle. The ink reservoir replenishes used ink in the ink chamber. The memory array 106 stores and provides the identification parameters for the thermal inkjet printhead 100. The identification parameters are typically provided during initialization of the printer and include color(s) of ink (e.g., black, green, red, blue), a number of nozzles on the thermal inkjet printhead, an addressing frequency, nozzle spacing, heating architecture, and the like.

Abstract: An enhanced services display message protocol (ESDMP) facilitates display of messages in a compliant analog telephony device (ATD). An exemplary gateway device in a voice over packet (VOP) network can activate enhanced services in a compliant ATD using the ESDMP and includes a controller and first and second interfaces. One of the interfaces can transmit and receive communications over a VOP network. The other interface can transmit and receive voice band message data modulated according to a frequency shift keying (FSK) protocol. The ESDMP can be used to configure the gateway to activate features supported by the ATD, to update call state information and to display feature state information.

Abstract: A simple to implement sample rate conversion system consisting of an input/output data flow controller, interpolation coefficient generation, and output data flow control to generate the converted data stream. Sample rate conversion may be done at real time video rates, without restrictions on the conversion ratios.

Abstract: A low power packet detector (LPPD) can significantly reduce the average power consumption of WLAN devices. The LPPD takes advantages of 802.11 protocols to turn on and off selected modules of an 802.11 receiver based on the packets on the medium and the decoding stages. The LPPD can be implemented mostly in firmware with minor hardware modifications to existing chips or be implemented in ASIC technology that takes full advantages of the power saving made possible by it.

Abstract: A method for arbitration grants access to an ultra high priority device if the ultra high priority device requests access. This access is limited to a selectable number of accesses. Thereafter the ultra high priority device is masked from requesting access for a selectable interval of time during which access may be granted to other devices. The number of assess and the interval of masking are preferably controlled by memory mapped data registers loaded into dedicated counters.

Abstract: The formation of a one time programmable (OTP) transistor based electrically programmable read only memory (EPROM) cell (100) is disclosed. The cell (100) includes multiple concentric rings (108, 110) out of which gate structures are formed. An inner transistor based cell (130) formed from the inner ring (108) is shielded from isolation material (106) by one or more outer rings (110). The lack of overlap between the inner transistor and any isolation material promotes enhanced charge/data retention by mitigating high electric fields that may develop at such overlap regions (30, 32).

Abstract: An embodiment of the instant invention is a method of providing a connection between a first conductor and a second conductor wherein the first conductor is situated under the second conductor and separated by a first insulating layer, the method comprising the steps of: forming an opening in the first insulating layer (layer 124 or 128 of FIGS. 1-4), the opening having a top, a bottom and sidewalls and is situated between the first conductor and the second conductor; forming a second insulating layer (layer 134, 138, and 142 of FIGS. 3 and 4) exclusively on the sidewalls of the opening thereby leaving a smaller opening in the first insulating layer; forming a conductive material (material 140 of FIGS. 3 and 4) in the smaller opening; and wherein the first insulating layer is comprised of a low-k material and the second insulating layer is comprised of an insulator which has electrical leakage properties which are less than the electrical leakage properties of the first insulating layer.

Abstract: The present invention provides a system for controlling isochronous data admission, within a WLAN system (102) that transports both isochronous and asynchronous data. The system includes an apparatus (300), functioning as an access point within a WLAN system. The apparatus comprises a memory (306) and a transceiver (312) communicatively coupled to the memory. The apparatus further comprises an access coordinator (302), communicatively coupled to the memory, and adapted to: evaluate actual access times of previous isochronous data streams, to determine projected access times needed by a new isochronous data stream, and to decide to admit or reject the new isochronous data stream based on an evaluation of the actual and projected access times.

Abstract: Multicarrier modulated communications, involving a transmitting modem (30; 30?) and a receiving modem (40; 40?) that operate according to normal operating mode and a low-power, quiescent, mode, are disclosed. In the quiescent mode, transmitter power is saved by scaling down the amplitude of the transmitted symbols in each frame by a scaling factor (A), and transmitting multiple instances of the frames in sequence. On receipt, the repeated frames are summed, and the summed amplitudes scaled to account for the repetition factor (M) and the scaling factor (A), to recover the transmitted information. If the repetition factor (M) is greater than or equal to the square of the scaling factor (A), the signal-to-noise ratio in quiescent mode is at least as high as that in normal operation. The repeating, scaling, and summing may all be performed in the frequency domain or in the time domain, as desired.

Abstract: In a target processor having a non-protected pipeline, the execution code is typically provided with interruptible code portions and with non-interruptible code portions. The non-interruptible code portions prevent implementation of a real time interrupt that would corrupt the code so that execution could not be resumed. A storage unit is provided that stores a signal permitting a code execution halt even during a non-interruptible code portion. In this manner, a program developer can determine the status of the processor at any point in the code execution. When the execution halt is initiated during a non-interruptible code segment, a bit is set in a bit position of a memory-mapped register. This bit position can be transferred from the target processor to the host processing unit during a transfer of status data.

Abstract: The present invention provides circuitry for writing to and reading from an SRAM cell core, an SRAM cell, and an SRAM device. In one aspect, the circuitry includes a write circuit coupled to the SRAM cell core that includes a write transistor gated by a write word line. The circuitry also includes a read buffer circuit coupled to the SRAM cell core to read the cell without disturbing the state of the cell. The read buffer circuit includes a read transistor gated by a read word line, the read transistor coupled between a read bit-line and a read driver transistor that is further coupled to a voltage source Vss. The read driver transistor and a first driver transistor of the cell core are both gated by one output of the cell core. The read transistor has an electrical characteristic that differs from that of the core cell first driver transistor.

Abstract: An integrated circuit device comprises internally on-chip an oscillator with a signal output. The device has a reference clock input, a first counter with a count input, a control input and a counter output, a second counter with a count input, a control input and an overflow indication output, and a test control logic circuit. The count input of the first counter is connected to the signal output of the oscillator. The count input of the second counter is connected to the reference clock input. The overflow indication output of the second counter is connected to an input of the test control logic circuit. The test control circuit has an output connected to the control input of the first counter to apply a stop counting control signal to the first counter after it has received an overflow indication signal from the second counter. The first counter after it has received a stop counting control signal provides a count at the counter output which is indicative of the output frequency of the oscillator.

Abstract: A switching regulation system and control scheme efficiently enables driving multiple loads from a common energy storage element, such as an inductor. The control scheme operates to store energy in the energy storage element over a first portion of a cycle, such as by ramping up current through an inductor, according to energy requirements of the multiple loads. After storing the energy in the storage element during the first portion of the cycle, the stored energy is delivered consecutively to each of the multiple loads over a subsequent portion of the cycle.

Abstract: A circuit and method for reducing the variation of a reference voltage as a function of resistivity ? in a current-mode bandgap reference circuit generating a reference current that is applied to an output resistor to generate the reference voltage. According to the invention, a substantially constant current is generated and added to the reference current.

Abstract: The interference cancellation (IC) system (500) includes a plurality of IC units, for which IC is applied. Each IC unit has its spread spectrum code generator, delay devices, correlators or matched filters (MF), spreading circuits and subtracting and adding devices. The IC process in accordance with the invention includes using a bank of MF to despread the received signal at every time instant corresponding to every identified multipath of every user's transmitted signal. Based on the despread signals, an initial decision for the present information symbol of every user can be made using a single-user receiver such as, for example, the conventional Rake receiver or an equalizer. Based on the initial decisions, IC regenerates the multipath signals for each user using timed versions of the spread spectrum code, the delays of the multipaths, and the corresponding channel medium estimates.