Abstract: A method of detecting interconnect defects in a semiconductor device. The method comprises positioning a portion of a semiconductor substrate, having a plurality of interconnects, in a field of view of an inspection tool. A voltage contrast image of the portion is produced. The voltage contrast image is obtained using a collection field that is at least about 1 percent different than an incident field. The method further comprises using the voltage contrast image to determine defective ones of the interconnects.

Abstract: A computing device 100 is provided that includes a graphic user interface (GUI) 104 and a processor 102 coupled to the GUI 104. The computing device 100 also includes a memory 106 coupled to the processor 102. The memory 106 stores a tabular application for execution by the processor 102, the tabular application providing, on the GUI 104, a tabular environment that supports both column rules and cell rules.

Abstract: An electronic device capable of graphical data analysis is provided. The device includes a processor capable of manipulating numerical data and a graphical data. An input is provided for issuing instructions to the processor to manipulate the numerical data and graphical data. The device includes a memory device, a software program, and an output. The memory device is for storing graphical data and numerical data. The software program is stored in the memory device and is operable for dynamically linking the numerical data and graphical data, such that when the numerical data is updated the software automatically updates the linked graphical data, and vice versa. The output is operable for displaying graphical data and numerical data.

Abstract: A device operable to maintain a document comprising a processor, a first problem space including a first variable having a first value, and a second problem space including a second variable having a second value, the first and second variables and the first and second values stored such that when the first variable is: the same as the second variable and the first value is different that the second value, the second value is maintained when the processor modifies the first value.

Abstract: An electronic device capable of graphical data analysis is provided. The device includes a processor capable of obtaining numerical data from graphical data, a storage device for storing numerical data, and an output for displaying numerical data.

Abstract: The present invention provides a method for forming a semiconductor device, as well as a semiconductor device. The method for manufacturing a semiconductor device, among others, includes providing a gate structure over a substrate, the gate structure including a gate electrode located over a nitrided gate dielectric, and forming a nitrided region over a sidewall of the nitrided gate dielectric.

Abstract: A system for, and method of, combined state- and phone-level pronunciation adaptation. One embodiment of the system includes: (1) a state-level pronunciation variation analyzer configured to use an alignment process to compare base forms of words with alternate pronunciations and generate a confusion matrix, (2) a state-level pronunciation adapter associated with the state-level pronunciation variation analyzer and configured to employ the confusion matrix to generate, in plural states, sets of Gaussian mixture components corresponding to alternative pronunciation realizations and enlarge the sets by tying the Gaussian mixture components across the states based on distances among the Gaussian mixture components and (3) a phone-level pronunciation adapter associated with the state-level pronunciation adapter and configured to employ phone-level re-write rules to generate multiple pronunciation entries. The phone-level pronunciation adapter may be embodied in multiple stages.

Abstract: The present invention provides a method for manufacturing a semiconductor device as well as a semiconductor device. The method, among other steps, may include forming a gate structure over a substrate, and forming a strain inducing sidewall spacer proximate a sidewall of the gate structure, the strain inducing sidewall configured to introduce strain in a channel region below the gate structure.

Abstract: A low-impedance output stage which operates from a low voltage power supply. In an embodiment, the output stage contains an operational amplifier and two PMOS transistors used in a feedback configuration resulting in low output impedance. The output stage may also include a capacitor connected between the output terminal of the output stage and the input of the PMOS transistor providing the output, resulting in an overall output impedance which remains low even at higher frequencies, thus enabling use of the output stage to drive capacitive loads without causing resonance.

Abstract: A method for dynamically switching hybrids during modem initialization to maximize channel capacity and performance includes the steps of evaluating each hybrid in the modem according to a cost function dependent on the quiet receive noise floor and the transmit signal echo, and then selecting the hybrid that results in the minimum value for the cost function. By performing these steps, the best available hybrid is selected in order to maximize channel capacity and hence maximize modem performance.

Abstract: The invention provides tester load board shields for attachment to tester load boards. The shields of the invention protect from physical damage and electromagnetic interference. A preferred embodiment of a tester load board shield of the invention is disclosed in which a disc and outer rim of conductive metal such as aluminum or aluminum alloy are configured to accept a tester load board. The tester load board shield has holes to align with a selected tester load board for attachment of the shield thereto. Stanchions are provided to facilitate attachment of the Loadboard with shield to automatic test equipment known in the arts while a tester load board, also familiar in the arts, is fastened to the shield. Another embodiment of a tester load board shield is disclosed in the shape of annulus configured to contain a tester load board within an outer rim planar surface and inner rim.

Abstract: A switch mode power converter is provided which includes a switching cell with a supply input, an output and a control input. A summing comparator has first and second differential input pairs and an output. The output is connected to the control input of the switching cell. An oscillator provides a periodic waveform that is applied to a first one of the inputs of the first differential input pair of the summing comparator. An adjustable reference voltage source provides an adjustable reference voltage a predetermined fraction of which is applied to a second one of the inputs of the first differential input pair of the summing comparator. An error amplifier has differential outputs coupled to the second pair of differential inputs of the summing comparator and a differential input pair.

Abstract: In accordance with an embodiment of the present invention an improved equalization system for DMT based modem receiver is provided. It includes a time domain equalizer for processing samples from an analog front end and includes a device for computing differences of time domain samples for every frame and the results are saved. An FFT is provided for calculating a first FFT and the results are saved in a FFT buffer so that at each DMT frame, after a difference and FFT operation, the FFT buffer contains the first FFT and v?1 time domain sample differences. A sliding FFT for each tone reads the first FFT result and v?1 FFTs and recursively computes the rest of v?1 FFTs for the particular tone. An equalizer is responsive to the computed sliding FFT for recursively computes equalizer outputs.

Abstract: A low noise AC coupled amplifier having transistors sharing bias currents, and having a low band-pass corner frequency and consuming low power. The amplifier may be used in a magneto-resistive (MR) preamplifier to amplify a response from a MR sensor. Bipolar and MOS transistors are used in the front end, utilizing the advantages of each transistor type to achieve low noise as well as low band-pass corner. The amplifier has a modified structure achieving lower power by using a PNP transistor instead of an NPN transistor.

Abstract: An area efficient stacked TCAM cell for fully parallel search. The TCAM cell includes a top half circuit portion interconnected with a replicated bottom half circuit portion such that there is a shared match line between each of the half circuit portions. Each TCAM cell includes a pair of memory elements that is connected to a pair of associated compare circuits such that the interconnections between the memory elements and the compare circuits are substantially vertical in active MOS layers and substantially horizontal in metal layers. The memory elements and the compare circuits are connected such that they facilitate shorter interconnections and sharing of terminals at the boundary of adjacent cells. The resulting stacked TCAM cell provides shorter match lines, shared bit lines, and reduced silicon area to facilitate improved routing and performance.

Abstract: A semiconductor wafer design and process having test pads (36) reducing cracks generated during the wafer saw process from extending into and damaging adjacent die. The present invention provides a plurality of circular test pads (36) in a wafer scribe street (34) such that any cracks generated in the test pad during wafer saw self terminate in the periphery of the circular test pad. By providing a curved test pad periphery, cracks will tend to propagate along the edges of the test pads and self terminate therein. The circular test pads avoid any sharp corners as is conventional in rectangular test pads which tend to facilitate the extension of cracks from corners to extend into the adjacent wafer die (32). The present invention utilizes existing semiconductor fab processing and utilizes new reticle sets to define the curved test pads.

Abstract: A clamping circuit containing a transistor and a current amplifier. The transistor is designed to turn on when the voltage at a node exceeds (falls below) a specified upper (lower) level. The current amplifier is designed to draw substantial amount of current when the transistor is turned on to clamp the voltage at the node to the desired level.

Abstract: A processor adapted to couple to external memory. The processor comprises a controller and data storage. The data storage is usable to store local variables and temporary data and is configurable to operate in either a cache policy mode in which a miss results in an access of the external memory or in a scratch pad policy mode in which a miss does not result in an access of the external memory. The data storage comprises first and second portions, and wherein only one of said portions is active at a time for storing said local variables. When the active portion does not have sufficient capacity for additional local variables, the other portion becomes the active portion for storing local variables. When one portion is the active portion, the other portion is used to store the temporary data and such other portion is sufficiently large to contain the temporary data.

Abstract: A method and apparatus for encoding video includes selecting a prediction motion vector for a current block of a current image frame from respective motion vectors of two or more neighbor blocks of the current block. Then the current block and a neighbor block corresponding to said prediction motion vector are checked to determine whether they are motion correlated. Checking motion correlation includes determining that the difference between the best correlation from the correlation of the current block with one or more neighbor blocks and the correlation of the neighbor block with a block in the previous image frame at a location defined by the prediction motion vector fulfils a predetermined criterion.

Abstract: The device for detecting and tracking a status of a device under laser trim includes: a series connected string of trim tracking links; and a plurality of detecting devices wherein each detecting device is coupled in parallel with a corresponding trim tracking link. This device allows detection of laser beam to work surface misalignment and the termination of lasing before critical active circuit components can be damaged.