Abstract: An integrated circuit chip packaging assembly having a first and second package side. An integrated circuit chip has a substrate side and an active circuit side. The chip includes integrated circuit devices formed on the active circuit side. The active circuit side of the chip is on the first package side. The die pad has at least one runner member extending therefrom, which may be bent toward the first package side. The active circuit side of the chip is attached to the die pad. The die pad is on the first package side relative to the chip. The package mold compound is formed over the die pad, at least part of the chip, and at least part of the runner member(s). At least part of the substrate side of the chip and/or at least part of the runner member(s) may not be covered by the package mold compound.

Abstract: A protection circuit for protecting an integrated circuit pad 201 against an ESD pulse, which comprises a discharge circuit having an elongated MOS transistor 202 (preferably pMOS) in a substrate 205 (preferably n-type), said discharge circuit operable to discharge the ESD pulse to the pad, to ground 203. The embodiment further contains a pump circuit connected to the pad for receiving a portion of the pulse's current; the pump circuit comprises a component 221 determining the size of this current portion (for example, another transistor, a string of forward diodes, or a reverse Zener diode), wherein the component is connected to ground. A discrete resistor 222 (for example about 40 to 60?) is connected between the pad and the component and is operable to generate a voltage drop (about 0.5 to 1.0 V) by the current portion.

Abstract: An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional circuits (702) on the integrated circuit and receive response test data from the functional circuits. A scan distributor circuit (800) receives serial test data from a peripheral bond pad (802) and distributes it to each parallel scan path. A scan collector circuit (844) collects test data from the parallel scan paths and applies it to a peripheral bond pad (866). This enables more parallel scan paths of shorter length to connect to the functional circuits. The scan distributor and collector circuits can be respectively connected in series to provide parallel connections to more parallel scan paths. Additionally multiplexer circuits (886,890) can selectively connect pairs of scan distributor and collector circuits together.

Abstract: The present invention jointly controls rate and power in a fashion that enables control of the two variables in one dimension. In some embodiments, this is done by ordering the possible transmit rate (320) and transmit power (340) combinations in a logical sequence that meets specific conditions. The present invention can first minimize the transmit time and then reduce the transmit power. The present invention can maintain the maximum rate possible that enables the receiving station to decode packets with an acceptable probability.

Abstract: A digital system without a color filter is provided. The desired color components are produced by a light source capable of emitting the desired color components. The color components are delivered to the pixels of the spatial light modulator through a group of optical lens and/or lightpipes, but without a color filter.

Abstract: An integrated circuit provides digital output signals in either single-ended or differential form on a shared set of pins. A control circuit generates signals to ensure that when one form (single-ended or differential) of outputs are being provided, outputs in the other form are disabled. Outputs in differential form may be provided at twice the frequency as compared to the outputs in single-ended form. As a result the same number of pins can be supported for both single-ended and differential outputs for a desired data throughput, and the pin count of the integrated circuit is reduced.

Abstract: Embodiments of the invention provide method for allocating CAZAC pilot (reference signal) sequences in multiple access OFDMA systems, or alternatively, in multiple access DFT-spread OFDM(A) systems (or SC-FDMA). Reference signal transmissions from different mobiles can either be distinguished by use of disjoint sub-carriers (frequency division orthogonality), or alternatively by use of distinct cyclic shifts of one base CAZAC sequence. In a wireless cellular network, neighboring cells should utilize different CAZAC sequences, in order to mitigate out-of-cell interference.

Abstract: In one aspect, the invention provides a method of fabricating a semiconductive device 200 that comprises forming a raised layer [510] adjacent a gate [340] and over a source/drain [415], depositing a silicidation layer [915] over the gate [340] and the raised layer [510], and moving at least a portion of the silicidation layer [915] into the source/drain [415] through the raised layer [510].

Abstract: The present invention provides a method for removing residue from a cavity during the formation of an interconnect structure, a method for manufacturing an interconnect structure using the same, and a method for manufacturing an integrated circuit using the same. The method for removing residue from a cavity during the formation of an interconnect structure, among other steps, may include subjecting residue (410) having an embedded metal therein located within a cavity (310) in a dielectric layer (240) and over at least a portion of a conductive feature (220) to a short duration oxidation process so as to oxidize a substantial portion of the embedded metal, and removing the residue (410) containing the oxidized embedded metal using an etch process.

Abstract: The present invention provides a method for manufacturing an interconnect and an integrated circuit. The method for manufacturing the interconnect, in one embodiment, includes forming a first metal feature (310) over a substrate, subjecting the first metal feature (310) to a hydrogen containing plasma (410), the hydrogen containing plasma (410) configured to remove organic residue (320) from an exposed surface of the first metal feature (310), and electroless depositing a second metal feature (510) on the first metal feature (310) having been subjected to the hydrogen containing plasma (410).

Abstract: In a method and system for testing an intermediary device, a tester provides a test signal to a device under test (DUT) via a first circuit path on the intermediary device. A first response is received from the DUT to verify that the DUT and the first circuit path are substantially free from defects. The DUT is configured to include a second circuit path to be tested. The test signal is provided by the DUT to the second circuit path. A second response is received from the DUT to verify that the second circuit path is substantially free from defects. In a similar manner, the DUT is configured to include additional components of the intermediary device to be tested.

Abstract: A method of reducing ringing artifacts in image data that has been filtered with a high frequency emphasis filter. For each filtered data value, a local variance is calculated from data values at neighboring filter taps. This variance is compared to a threshold, and if the threshold is exceeded, the filtered data value is limited between local minimum and maximum values. A method of reducing noise, also using the local variance, is also described.

Abstract: The formation of one or more accumulation mode multi gate transistor devices is disclosed. The devices are formed so that short channel effects are mitigated. In particular, one more types of dopant materials are implanted in a channel region, an extension region and/or source/drain regions to mitigate the establishment of a conduction path and the accumulation of electrons in the channel region that can result in an unwanted leakage current.

Abstract: A method of forming an integrated circuit transistor (50). The method provides a first semiconductor region (52) and forms (110) a gate structure (54x) in a fixed position relative to the first semiconductor region. The gate structure has a first sidewall and a second sidewall (59x). The method also forms at least a first layer (58x, 60x) adjacent the first sidewall and the second sidewall. The method also forms (120) at least one recess (62x) in the first semiconductor region and extending laterally outward from the gate structure. Additional steps in the method are first, oxidizing (130) the at least one recess such that an oxidized material is formed therein, second, stripping (140) at least a portion of the oxidized material, and third, forming (160) a second semiconductor region (66x) in the at least one recess.

Abstract: A single sleep mode controller which ensures that there is at least a corresponding minimum voltage level across capacitors when the corresponding regulators are turned off. In an embodiment, the sleep mode controller uses a single comparator which compares the voltages across capacitors in a time division multiplexed (TDM) manner, and initiates the charging operation for the capacitor if the voltage level falls below a corresponding minimum voltage level. The sleep mode controller continues the charging operation until the voltage level exceeds a corresponding upper threshold value. Due to the use of the single controller, power and/or space savings may be attained.

Abstract: A one time programmable (OTP) electrically programmable read only memory (EPROM) transistor (100) having an increased breakdown voltage (BVdss) is disclosed. The increased breakdown voltage reduces the probability that the OTP EPROM (100) will breakdown during a programming operation by maintaining a breakdown voltage above a programming voltage. The breakdown voltage is, at least partially, increased by forming a p-doped region (140) within a semiconductor substrate (102), and forming a drain region (166) of the OTP EPROM (100) within the p-doped region (140).

Abstract: An apparatus for use with a digital micro-mirror includes a hinge disposed outwardly from a substrate. The hinge is capable of at least partially supporting a micro-mirror disposed outwardly from the hinge. The micro-mirror is capable of being selectively transitioned between an on-state position and an off-state position. In one particular embodiment, the hinge comprises a substantially flat profile for at least a portion of the hinge disposed between a first hinge post of the hinge and a mid-point of the hinge. The apparatus also includes a plurality of process control voids formed within a conductive layer disposed inwardly from the hinge. In one particular embodiment, the substantially flat profile is at least partially created from the plurality of process control voids.

Abstract: Detection for a MIMO (multiple-input, multiple-output) wireless communications system with symbols iteratively detected in subsets with maximum likelihood hard decisions within subsets. Previously detected subsets of symbols are used to regenerate corresronding input signals for interference cancellation. With a 4-transmitter antenna, 4-receiver antenna system, two subsets of two symbols are possible with the first two symbols detected with zero-forcing or MMSE soft estimates which feed maximum likelihood hard decisions; and the hard decision for the first two symbols are used for interference cancellation followed by zero-forcing or MMSE soft estimates for the second two symbols which then feed further maximum likelihood hard decisions.

Abstract: A pre-ECD surface treatment. After forming the barrier material (110) and seed layer (112), the surface of the seed layer (112) is treated with an H2 plasma to remove surface contamination (122), reduce any CuOx (123), and improve wettability. The ECD copper film (124) is then formed over the seed layer (112).

Abstract: One aspect of the invention relates to a method of cleaning high density capacitors. According to the method, the capacitors are cleaned with a plasma that includes fluorine-containing radicals. The plasma removes a small layer from the capacitors, including their sidewalls, and thereby removes surface contaminants. The method is effective even when the capacitors include hard-to-etch dielectric materials, such as tantalum and hafnium oxides. In a preferred embodiment, the plasma clean is combined with a solvent clean.