Abstract: A method of producing an image comprising impinging a beam of light on first region of a dynamic filter. The dynamic filter comprising at least two regions having different light transmission characteristics. A first region of the dynamic filter transmits a first transmitted portion of the beam of light and reflects a first reflected portion of the beam of light. Impinging at least some of the first reflected portion of the beam of light on a second region of the dynamic filter. The second region of the dynamic filter transmitting a second transmitted portion. The first and second transmitted portions are modulated.

Abstract: A method of tracing a data processor upon reset of the data processor. A data processor reset signal resets the data processor, part of trace collection hardware and does not reset remaining parts of trace collection hardware. The data processor reset signal may be not owned, owned by an application program or owned by a debugger. The partial not reset of the trace collection hardware occurs only upon a data processor reset signal owned by the debugger. A trace logic reset signal resets both the data processor and the trace collection hardware when not owned. This trace logic reset signal resets the data processor only when owned by the debugger and resets the trace collection hardware when owned by an application program.

Abstract: A network configuration (10) including a first network medium which is a 1394 network as well as a second network medium. Each of the first and second network media is coupled to a corresponding plurality of host computers (H1 through H3 and H5 through H7). The network configuration further includes a link layer gateway computer (H4) coupled to both the first network medium and the second network medium. The link layer gateway computer is operable to communicate a data packet from a source host computer selected from one of the plurality of host computers coupled to the first network medium to a destination host computer selected from one of the plurality of host computers coupled to the second network medium.

Abstract: A pre-ECD surface treatment. After forming the barrier material (110) and seed layer (112), the surface of the seed layer (112) is treated with an H2 plasma to remove surface contamination (122), reduce any CuOx (123), and improve wettability. The ECD copper film (124) is then formed over the seed layer (112).

Abstract: The present invention provides a method for implanting ions in a substrate and a method for manufacturing an integrated circuit. The method for implanting ions in a substrate, among other steps, including placing a substrate (410) on an implant platen (405) such that a predominant axes (430) of the substrate (410) is rotated about 30 degrees to about 60 degrees or about 120 degrees to about 150 degrees offset from a radial with respect to the implant platen (405), and further wherein the substrate (410) is not tilted. The method further includes implanting ions into the substrate (410), the rotated position of the predominant axes (430) reducing shadowing.

Abstract: One aspect of the invention relates to a method of cleaning high density capacitors. According to the method, the capacitors are cleaned with a plasma that includes fluorine-containing radicals. The plasma removes a small layer from the capacitors, including their sidewalls, and thereby removes surface contaminants. The method is effective even when the capacitors include hard-to-etch dielectric materials, such as tantalum and hafnium oxides. In a preferred embodiment, the plasma clean is combined with a solvent clean.

Abstract: An on-chip receiver sensitivity test mechanism for use in an integrated RF transmitter wherein the transmitter and the receiver share the same oscillator. The mechanism obviates the need to use expensive RF signal generator test equipment with built-in modulation capability and instead permits the use of very low cost external RF test equipment. The invention utilizes circuitry already existing in the transceiver, namely the modulation circuitry and local oscillator, to perform sensitivity testing. The on-chip LO is used to generate the modulated test signal that otherwise would need to be provided by expensive external RF test equipment with modulation capability. The modulated LO signal is mixed with an externally generated unmodulated CW RF signal to generate a modulated signal at IF which is subsequently processed by the remainder of the receiver chain. The recovered data bits are compared using an on-chip BER meter or counter and a BER reading is generated.

Abstract: A micromirror array fabricated on a semiconductor substrate. The array is comprised of three operating layers. An addressing layer is fabricated on the substrate. A hinge layer is spaced above the addressing layer by an air gap. A mirror layer is spaced over the hinge layer by a second air gap. The hinge layer has a hinge under and attached to the mirror, the hinge permitting the mirror to tilt. The hinge layer further has spring tips under the mirror, which are attached to the addressing layer. These spring tips provide a stationary landing surface for the mirror.

Abstract: One embodiment provides an anchor to hold getter materials in place within a micromechanical device package substrate, said anchor comprising: a first cavity face; and a second cavity face. The cavity faces define an anchor cavity and mechanically retain a getter away from a region holding the micromechanical device. Another embodiment provides an anchor to hold a getter in place within a micromechanical device package. The anchor comprises: a package substrate; and a member attached to the package substrate, the member shaped to provide mechanical retention of the getter material formed over said member. Another embodiment provides a micromechanical device package comprising: a package substrate; a package lid enclosing a package cavity; a micromechanical device in the package cavity; and a getter anchor in the package cavity. Other embodiments provide methods of packaging and forming packages having a getter anchor. One getter anchor is formed in a substrate 906 comprised of at least three layers.

Abstract: The present invention provides, for use in a semiconductor manufacturing process, a method (100) of preparing an ion-implantation source material. The method includes providing (110) a deliquescent ion implantation source material and mixing (110) the deliquescent ion implantation source material with an organic liquid to form a paste.

Abstract: Disclosed herein is a method of projecting images using light valves. Pixel patterns generated of the light valve pixels based on image data are projected at different locations at a time.

Abstract: In one aspect, the invention provides a method of fabricating a semiconductive device [200], comprising siliciding a gate [340] with a first silicidation layer [710], removing a protective layer [510] to expose source/drains [415], and siliciding the gate [340] and the source/drains [415] with a second silicidation layer.

Abstract: The invention provide methods for classifying user equipments (UEs) communicating with a serving base station (Node B) according to their experienced average interference in subsets of frequency or time resources. The classification utilizes existing channel quality indication (CQI) reports the UEs send to their serving Node B for the purposes of data scheduling. Multiple CQI reports are averaged to practically eliminate short term variations caused by fast fading and capture the long term interference and signal-to-interference and noise ratio (SINR) that the UEs experience. By capturing this average interference and SINR, a reference Node B can apply interference co-ordination through fractional frequency reuse or fractional time reuse.

Abstract: A ferroelectric memory capacitor is formed by forming a barrier layer, a first metal layer, a ferroelectric layer, a second metal layer, and a hard mask layer, on dielectric layer (70). Using the patterned hard mask layer (255), the layers are etched to form an etched barrier layer (205), and etched first metal layer (215), and etched ferroelectric layer (225), and etched second metal layers (235, 245). The etched layers form a ferroelectric memory capacitor (270) with sidewalls that form an angle with the plane of the upper surface of the dielectric layer (70) between 78° and 88°. The processes used to etch the layers are plasma processes performed at temperatures between 200° C. and 500° C.

Abstract: The present invention provides a current-sense bias circuit for use with a magnetoresistive head. In one embodiment, the current-sense bias circuit includes a voltage biasing portion configured to provide a bias voltage across the magnetoresistive head thereby establishing a bias current through the magnetoresistive head. Additionally, the current-sense bias circuit also includes a current sensing portion coupled to the voltage biasing portion and configured to sense a change in the bias current based on a resistivity change of the magnetoresistive head.

Abstract: A torsional hinged resonant device having an improved anchor support for providing inertia drive. The area by the anchors connecting the torsional hinges to the support member are thinned to have a reduced cross section. The reduced or thinned area increases flexibility such that less force is required to generate a desired angular rotation.

Abstract: A method for determining the anti-reflective coating (or bottom anti-reflective coating) over-etch time adjust with real-time process feedback is presented. The critical dimension CDresist of the patterned photoresist is measured and a first wafer with median values chosen (101) from a lot. A first time t* is found (102) and used to form the desired structure. Using the measured critical dimension of the formed structure on the first wafer a second time tlot is found (104). Finally, an over-etch time t(x) is found and used to etch the remaining wafers in the lot (106).

Abstract: A method (10) of forming a MIM (metal insulator metal) capacitor is disclosed whereby adverse affects associated with copper diffusion are mitigated even as the capacitor is scaled down. A sidewall spacer (156) is formed against an edge (137) of a layer of bottom electrode/copper diffusion barrier material (136), an edge (151) of a layer of capacitor dielectric material (150) and at least some of an edge (153) of a layer of top electrode material. The sidewall spacer (156) is dielectric or non-conductive and mitigates “shorting” currents that can develop between the plates as a result of copper diffusion. Bottom electrode diffusion barrier material (136) mitigates copper diffusion and/or copper drift, thereby reducing the likelihood of premature device failure.

Abstract: A method of packing electronic devices and an apparatus thereof are disclosed herein. The method allows for usage of solder materials with a melting temperature of 180° C. or higher, such as from 210° C. to 300° C., and from 230° C. to 260° C., so as to provide reliable and robust packaging. This method is particularly useful for packaging electronic devices that are sensitive to temperatures, such as microstructures, which can be microelectromechanical devices (MEMS), such as micromirror array devices.

Abstract: Disclosed herein is a projection system that comprises an illumination system providing incident light, a projection lens for directing the incident light onto one or more spatial light modulator from where the incident light is modulated in accordance with a stream of image data derived from the desired image, and a projection lens for projecting the modulated light onto a screen.