Abstract: Disclosed herein is a micromirror device having a reflective mirror plate with reduced dimensions. The micromirror device can be a member of an array of micromirror devices for use in optical signal modulations, such as display applications and optical signal switching applications.

Abstract: A method and circuit for eliminating input voltage offset in an amplifier circuit are provided. An exemplary offset correction circuit is configured with DC restoration to eliminate the DC input voltage offset by suitably providing a correction voltage to correct an input voltage offset during operation of the amplifier circuit, without realizing recovery time problems associated with AC coupling. An exemplary offset correction circuit is configured with DC restoration and comprises a timing circuit, a sample and hold circuit, and a feedback circuit to provide a correction voltage signal to correct input voltage offset. The timing circuit is configured to determine a “dead time” and “live time” for operation of the amplifier circuit. During the “dead time” period the sample and hold circuit will sample a differential signal across the DC coupling and provide a feedback signal through feedback circuit to correct input offset voltage.

Abstract: A method for making a transistor within a semiconductor wafer. The method may include etching a recess at source/drain extension locations 90 and depositing SiGe within the recess to form SiGe source/drain extensions 90. Dopants are implanted into the SiGe source/drain extensions 90 and the semiconductor wafer 10 is annealed. Also, a transistor source/drain region 80, 90 having a SiGe source/drain extension 90 that contains evenly distributed dopants, is highly doped, and has highly abrupt edges.

Abstract: A prefilter is trained as follows. The frequency response B of a conditioned channel is determined without reference to the prefilter, and the frequency response W of the prefilter is computed from the frequency response B of the conditioned channel.

Abstract: A reduced search space minimum distance decoding algorithm provides average probability of error performance close to that of optimal MAP decoding. The decoding algorithm provides dramatic complexity reductions compared with MAP decoding. A sub-optimal decoder receives signal vectors y1 . . . yk. Soft output bits are generated as is a reduced search space V via a reduced search space table creation unit in response to the soft output bits and an estimated channel H. A signal vector b is generated via a maximum likelihood decoding unit in response to the reduced search space V and the signal vectors y1 . . . yk.

Abstract: Systems, methods and circuits for implementing efficient device testing. As one example, a method is disclosed for testing a device that includes both a digital and analog portion. In some cases, the digital portion includes a plurality of latch devices, and the analog portion includes a plurality of memory cells and a plurality of selector devices. Each of the plurality of selector devices is electrically coupled to a respective one of the memory cells, is at least indirectly coupled to one of the plurality of latch, devices, and is controlled by a selector input. In the method, a load clock is applied to the plurality of latch devices such that a pattern is loaded into the plurality of latch devices. The selector input is asserted such that a derivative of the pattern is received by the plurality of selectors and returned to the plurality of latch devices. A system clock is applied to the plurality of latch devices such that the derivative of the pattern is loaded into the plurality of latch devices.

Abstract: Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.

Abstract: The present invention pertains to formation of a transistor in a manner that mitigates overlap capacitances, thereby facilitating, among other things, enhanced switching speeds. More particularly, a gate stack of the transistor is formed to include an optional layer of poly-SiGe and a layer of poly-Si, where at least one or the layers comprises carbon. The stack may also include a polysilicon seed layer that can also comprise carbon. The carbon changes the components of sidewall passivation materials and affects etch rates during an etching process, thereby facilitating isotropic etching. The changed passivation materials coupled with an enhanced sensitivity of the poly-SiGe and carbon-doped poly-SiGe layer to an etchant utilized in the etching process causes the stack to have a notched appearance.

Abstract: A new system and method is described, utilizing a scheduler based on a transmission power consumption calculation and prioritizing algorithm. The system utilizes the (APSD) protocol specified in the 802.11e draft for saving power in wireless local area networks. The system comprises an access point having a priority queue, one or more stations, an APSD frame comprising an association ID for identifying one of the stations and a scheduled wake-up time for the identified station. An algorithm is employed for calculating the total transmission power consumption of downlink data for the stations. The AP originates and transmits to the one or more stations the APSD frame of the scheduled activation delay time. The current data to be transmitted to each station is accessed by the algorithm to determine the total transmission power consumption to each station.

Abstract: A semiconductor device with a chip (505), its position defining a plane, and an insulating substrate (503) with first and second surfaces; the substrate is substantially coplanar with the chip, without warpage. One of the chip sides is attached to the first substrate surface using adhesive material (504), which has a thickness. The thickness of the adhesive material is distributed so that the thickness (504b) under the central chip area is equal to or smaller than the material thickness (504a) under the peripheral chip areas. Encapsulation compound (701) is embedding all remaining chip sides and the portions of the first substrate surface, which are not involved in the chip attachment. When reflow elements (720) are attached to the substrate contact pads, they are substantially coplanar with the chip.

Abstract: An ESD protection device can include a silicon-controlled rectifier (SCR) and an external pumping circuit. The external pumping circuit can be used to forward bias a junction of the SCR. The external pumping circuit can comprise a transistor that can be coupled to a region of the SCR to pump the region.

Abstract: An apparatus is for detecting body diode conduction in a semiconductor device that includes first regions fixed with a substrate having an upper surface to establish a source, gate and drain with drain-to-source current flow parallel with the surface. The first regions experience body diode conduction in a first inter-region current flow among first involved regions. The apparatus includes: second regions fixed with the substrate and substantially similar in relative size and placement with respect to other second regions as a corresponding first region is in relative size and placement with respect to other first regions. The second regions experience model body diode conduction in a second inter-region current flow among second involved regions. The model body diode conduction occurs generally contemporaneously with the body diode conduction. Selected second regions are coupled with selected first regions to establish a connection locus to permit detecting the model body diode conduction.

Abstract: A method and system for conserving power in a WLAN receiver is provided by a channel estimator for detecting transmitted errors in a transmitted packet and providing equalization for the detected channel errors; a separate pilot processor for detecting off set errors from the channel estimation and providing off set correction to said equalization for the whole data portion of the packet after the preamble and a control response to the start of each packet for enabling said channel estimator during the preamble and thereafter disabling said channel estimator for the remainder of the packet and storing the estimated value.

Abstract: A memory circuit and method to reduce array noise due to wordline coupling is disclosed. The circuit includes a plurality of memory cells arranged in rows (702, 704, and 706) and columns (750, 752). Each row has a first part (1102) and a second part (1108). A first conductor (750) is coupled to a respective column of memory cells in each first part. A second conductor (752) is coupled to a respective column in each second part. A third conductor is coupled to a control terminal of each memory cell in the first part (1102) of a first row and the second part (1108) of a second row.

Abstract: The leakage current of an OTP-EPROM cell formed using buried channel PMOS technology can be reduced. The reduction in leakage current of the OTP-EPROM can be achieved by blocking implantation of the Vtp implant into a channel region of an n-well that substantially underlies a floating gate structure. The Vtp implant can be blocked by providing a mask overlying the surface of the channel region of the n-well during implantation of the Vtp implant.

Abstract: The present invention provides, in one embodiment, a semiconductor wafer (100) dicing process. The dicing process comprises removing circuit features (120) from a street (115) located between dies (105) on a semiconductor substrate (102) using a first blade (135), such that the semiconductor substrate is exposed, and cutting through the exposed semiconductor substrate using a second blade (190). The first blade has a surface (140) coated with an abrasive material (145) comprising grit particles (150), having a median diameter (155) of at least about 25 microns. The grit particles are adhered to the first blade with a bonding agent (160) having a hardness of about 80 or less (Rockwell B Hardness scale). The grit particles have a concentration in the bonding agent ranging from about 25 to about 50 vol %. Another embodiment of the invention is a method of manufacturing a semiconductor device (200).

Abstract: A novel mechanism for performing high accuracy cable diagnostics. The mechanism utilizes time domain reflectometry (TDR) to detect and identify cable faults, perform estimations of cable length, identify cable topology, identify load and irregular impedance on metallic paired cable, such as twisted pair and coaxial cables. The TDR mechanism transmits pulses whose shapes are programmable and analyzes the signal reflections. The shapes of the pulses transmitted can be optimized in accordance with the channel characteristics. Further, the TDR mechanism is adapted to operative in the presence of high pass filters in the channel.

Abstract: The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises depositing a protective layer (510) over a spacer material (415) located over gate electrodes (250) and a doped region (255) located between the gate electrodes (250), removing a portion of the spacer material (415) and the protective layer (510) located over the gate electrodes (250). A remaining portion of the spacer material (415) remains over the top surface of the gate electrodes (250) and over the doped region (255), and a portion of the protective layer (510) remains over the doped region (255). The method further comprises removing the remaining portion of the spacer material (415) to form spacer sidewalls on the gate electrodes (250), expose the top surface of the gate electrodes (250), and leave a remnant of the spacer material (415) over the doped region (255).

Abstract: The preferred embodiments of the present invention provide approaches for synchronizing signals in a testing system. In some embodiments, the timing signal associated with each device under test (DUT) is maintained at an integer multiple of the tester timing signal. Additionally, in other embodiments, the timing signal associated with various DUTs is used as a timing reference for other devices.

Abstract: A method of power consumption reduction in integrated circuits comprising extensive use of differential signaling within said circuits. Differential signaling comprises a pair of coupled, symmetrically opposite and operatively dependent electronic signals each driven by voltages of the same magnitude, but of opposite polarity with respect to a common ground. The drive voltages of each signal are of relatively low potential as compared to the core operating voltage of present day devices. The low-voltage pair of signals tends to create offsetting fields of electromagnetic interference from the flow of current within their respective conductors which tends to minimize inductive effects (and therefore corruption of signals) in adjacent signal lines. Differential signaling replaces all or as many single-end signals as possible throughout the device resulting in relatively lower power usage as compared to present devices.