Abstract: The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises depositing a protective layer (510) over a spacer material (415) located over gate electrodes (250) and a doped region (255) located between the gate electrodes (250), removing a portion of the spacer material (415) and the protective layer (510) located over the gate electrodes (250). A remaining portion of the spacer material (415) remains over the top surface of the gate electrodes (250) and over the doped region (255), and a portion of the protective layer (510) remains over the doped region (255). The method further comprises removing the remaining portion of the spacer material (415) to form spacer sidewalls on the gate electrodes (250), expose the top surface of the gate electrodes (250), and leave a remnant of the spacer material (415) over the doped region (255).

Abstract: A leadframe for use in the assembly of integrated circuit chips comprising a base metal structure having an adherent layer of nickel covering said base metal; an adherent film of palladium on said nickel layer; and an adherent layer of palladium on said palladium film, selectively covering areas of said leadframe suitable for bonding wire attachment and solder attachment.

Abstract: A method for removing dielectric material 50 from a semiconductor wafer 20 that contains metal silicide 60 or 90. The method includes performing a selective etch 202 of the semiconductor wafer 20 using an organic semi-aqueous solvent-based etchant until the dielectric material 50 is substantially removed and then rinsing 204 the semiconductor wafer 20 including a surface, 63 or 93, of the metal silicide, 60 or 90 respectively, of the semiconductor wafer 20.

Abstract: There is provided a burn-in monitor for testing modules on an Integrated Circuit (IC), and a corresponding method. The burn-in monitor comprises: a Serial Test and Configuration Interface STCI for controlling and observing modules through a scan chain; a scan-in pin for loading a prepared set of test vectors; and a scan-out pin associated with the STCI for outputting all status bits. A burn-in mode is provided on the STCI and is selectable during testing for configuring the scan chain, such that said scan chain contains only those status bits required for monitoring burn-in, plus a number of bits necessary for controlling overall behaviour of the scan chain whereby the scan elements associated with the control bits will be loaded with zero. Hence the scan-out pin will show a one if there is a fault. Preferably the scan chain contains the minimum number of control bits necessary for controlling overall behaviour of the scan chain.

Abstract: An apparatus for applying write signals including a first write signal and a second write signal to write information to a memory device includes a current directing circuit receiving the write signals and directing a write current to establish a write voltage between first and second write loci in a first or second excursion toward a first or second polarity in response to the first or second write signal. The first and second write loci are coupled with supply locus via an adjacent first or second impedance unit and a first or second switching unit. The first and second switching units are controlled at first and second control loci by the first and second write signals. First and second boost systems are coupled with the first and second control loci for boosting the write voltage toward the first and second polarities during first and second excursions.

Abstract: In accordance with the teachings of the present invention, a semiconductor device having voltage output function trim circuitry and a method for the same are provided. In a particular embodiment, the method includes electrically coupling to a main circuit of a semiconductor device a plurality of resistances each operable to determine a different output voltage range of the main circuit, electrically coupling each of the plurality of resistances to a respective one of a plurality of fuses, electrically coupling each of a plurality of fuses to a respective one of a plurality of function trim pads, and electrically decoupling all but one of the plurality of resistances by applying a respective current between the respective function trim pads and an output node sufficient to open the respective fuses.

Abstract: The present invention facilitates semiconductor fabrication of semiconductor devices having polysilicon resistors. An oxide layer is formed over a semiconductor device (104). A polysilicon layer is formed on the oxide layer (106). The polysilicon layer is patterned to form a polysilicon resistor (108). A poly resistor mask having a selected percentage of the poly resistor exposed is formed on the poly resistor (110). A selected dopant is implanted (112), which modifies the resistivity of the poly resistor. The mask is removed (114) and a thermal activation process is performed (116) that diffuses the implanted dopant to a substantially uniform concentration throughout the polysilicon resistor.

Abstract: Method and structure for mounting a torsional hinged device, such as a mirror, having a first TCE (thermal coefficient of expansion) on a substrate having a second TCE different than said first TCE. The structure comprising a plurality of compliant support posts between the substrate and the torsional hinged device that deform when the contraction and/or expansion of the torsional hinged device is different than the corresponding contraction and expansion of the substrate.

Abstract: A circuit (90) and method are presented to accurately determine a BEMF voltage of a VCM coil (20) after termination of a driving current in a first current direction in the coil (20). The circuit includes a circuit for activating selected VCM coil driver transistors (44–47) to apply a current to the coil (20) in a direction opposite the first current direction to generate a magnetic field to oppose eddy currents established in structures adjacent the coil (20) by the driving current. The time that the eddy current opposing current may be applied may be determined, for example, by determining a magnitude of the original current command, a time that the coil spends in flyback, or a magnitude of the original driving current, and adjusting the time of application of the eddy current opposing current accordingly.

Abstract: A primary current circuit 42 that outputs a primary current IPTAT proportional to the primary coefficient of temperature, secondary current circuit 43 outputs a secondary current IPTAT2 proportional to the Nth (N: an integer of 2 or larger) coefficient of temperature based on the primary current, constant current source 41 that supplies current to the primary and secondary currents, and power control switch Q11 that shuts down the voltage supply based on a rise in the secondary current.

Abstract: A vertical wafer boat for supporting at least one semiconductor wafer, formed by a process includes forming a plurality of angled support grooves into a plurality of support members with a groove-making machine. Each support member extends along a longitudinal axis and each of the support grooves is spaced apart from one another and extend generally obliquely into the respective support member with respect to the longitudinal axis. The groove-making machine is positioned at a nonperpendicular angle with respect to the longitudinal axis, and thus defines an angled tooth between adjoining support grooves to support at least one wafer, and each support groove includes top and bottom corners inside a base portion that are generally supplementary with respect to each other. Top and bottom portions of the plurality of members are joined to top and bottom end plates that oppose each other respectively, to form the wafer boat.

Abstract: The present invention provides, in one aspect, a method of conditioning a deposition chamber 100. An undercoat is placed on the walls of a deposition chamber 100 and a pre-deposition coat is deposited over the undercoat with a plasma gas mixture conducted at a high pressure and with high gas flow.

Abstract: A system and method of dynamic offset compensation that is particularly adaptable to analog-to-digital conversion performed in control applications employing highly integrated Digital Signal Processor (DSP) devices. The system providing dynamic compensation of Analog-to-Digital Converter (ADC) zero level offset errors includes an integrated DSP device with a multi-bit ADC and a PWM waveform generator for producing at least one PWM output, and an external low pass filter. The ADC receives an analog input signal and converts it into a corresponding digital output signal. The DSP device measures the zero level offset of the ADC output signal, and dynamically controls characteristics of the PWM output based on the measured offset. The low pass filter receives the PWM output and applies a corresponding controlled DC output voltage to the low reference voltage input of the ADC to dynamically compensate for the zero level offset error.

Abstract: A differential bus network, in general, or a controller area network (CAN) driver, in particular, controls and minimizes the variation on the common-mode signal of the CAN bus. This CAN driver also provides improved symmetry between its differential output signals, CANH and CANL, and provides protection for its low voltage devices from voltage transients occurring on its output lines. The common-mode signal is sensed and buffered, then during the dominant to recessive transition, the bus signals are shorted to the buffered common mode voltage. Specifically, additional switches or transistors are used to pull the differential output signals, CANH and CANL, to the common mode signal VCM when the state of the CAN bus transitions from dominant to recessive. This improvement minimizes high frequency spikes in the common-mode signal and eliminates DC shifts during transitions of the state of the CAN bus.

Abstract: A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the boundary of the core and provides a way to test the core and the interconnections between cores. The test architecture enables each of the plural wrappers in the IC, including wrappers in cores embedded within other cores, with separate enable signals.

Abstract: Lubricants for lubricating surfaces of microelectromechanical devices are disclosed. Specifically, the lubricants can be applied to the contacting surfaces of the microelectromechanical devices so as to remove stiction of the contacting surfaces.

Abstract: According to one embodiment of the invention, a chemical mechanical polishing system includes a platen having a first surface adapted to couple a polishing pad thereto. The first surface includes a generally circular center portion and an annular portion surrounding the generally circular center portion. The generally circular center portion encloses an area and has an attachment surface area that is less than the area enclosed by the generally circular center portion. The attachment surface area is adapted to couple an inner portion of the polishing pad to the platen. According to one embodiment of the invention, a chemical mechanical polishing system includes a platen having a first surface coupling a polishing pad thereto. The first surface includes a generally circular center portion and an annular portion surrounding the generally circular center portion.

Abstract: According to one embodiment, a method for providing position feedback for a device includes providing a photointerrupter having a light-emitting diode, a phototransistor, and an aperture between the light-emitting diode and the phototransistor. For a given size aperture, a current through the phototransistor is a function of a current through the light-emitting diode. The method also includes controlling the current through the light-emitting diode current such that a change in the effective aperture size results in a desired approximately proportional change in current through the phototransistor. While controlling the current through the light-emitting diode, a portion of the aperture is blocked by an arm that has a position indicative of the position of the device. The method also includes providing a signal indicative of the change in current through the photodiode as an indication of the change in position of the device.

Abstract: An amplifier circuit includes first (7A) and second (7B) operational amplifiers connected in a parallel configuration. A first terminal (12) of a first input resistor (5) is coupled to one input of both of the first (7A) and second (7B) amplifiers. A first terminal (15) of a second input resistor (6) is coupled to another input of both of the first (7A) and second (7B) amplifiers. A differential input voltage is applied between the second terminals of the first and second input resistors. The output signals of the first (7A) and second (7B) operational amplifiers are combined to produce an output signal (11AB) representative of feedback currents produced in the first (5) and second (6) input resistors. Upper and lower common mode input voltage ranges associated with the differential input voltage extend substantially above and below the upper and lower supply voltages, respectively, of the amplifier circuit.

Abstract: The present invention provides a system (100) for aligning a dispensing apparatus (110) utilized within a semiconductor deposition chamber (102). A stationary reference apparatus (106) is disposed along the bottom of the deposition chamber. A self-alignment support system (122), comprising one or more support components (124), is intercoupled between the dispensing apparatus and a deposition system exterior component (112). The self-alignment support system is adapted to facilitate and secure repositioning of the dispensing apparatus responsive to pressure applied to the dispensing surface (114) thereof. A non-yielding offset component (126) is placed upon a first surface (108) of the stationary reference apparatus. The dispensing surface of the dispensing apparatus is engaged with the offset component, and pressure is applied to the dispensing apparatus via the offset component until a desired alignment is achieved.