Abstract: An amplifier circuit includes first (7A) and second (7B) operational amplifiers connected in a parallel configuration. A first terminal (12) of a first input resistor (5) is coupled to one input of both of the first (7A) and second (7B) amplifiers. A first terminal (15) of a second input resistor (6) is coupled to another input of both of the first (7A) and second (7B) amplifiers. A differential input voltage is applied between the second terminals of the first and second input resistors. The output signals of the first (7A) and second (7B) operational amplifiers are combined to produce an output signal (11AB) representative of feedback currents produced in the first (5) and second (6) input resistors. Upper and lower common mode input voltage ranges associated with the differential input voltage extend substantially above and below the upper and lower supply voltages, respectively, of the amplifier circuit.

Abstract: The present invention provides a system (100) for aligning a dispensing apparatus (110) utilized within a semiconductor deposition chamber (102). A stationary reference apparatus (106) is disposed along the bottom of the deposition chamber. A self-alignment support system (122), comprising one or more support components (124), is intercoupled between the dispensing apparatus and a deposition system exterior component (112). The self-alignment support system is adapted to facilitate and secure repositioning of the dispensing apparatus responsive to pressure applied to the dispensing surface (114) thereof. A non-yielding offset component (126) is placed upon a first surface (108) of the stationary reference apparatus. The dispensing surface of the dispensing apparatus is engaged with the offset component, and pressure is applied to the dispensing apparatus via the offset component until a desired alignment is achieved.

Abstract: A media player coupled to a network contains a processor, non-volatile memory, volatile memory, a driver, and input and output ports. The media player receives a media file over the network that contains an encoded media stream and a universal decoder. The player's processor converts or translates (or otherwise generates) the universal decoder into a player-specific decoder which may differ from the universal decoder. A library of routines stored in the non-volatile memory is used to create the player-specific decoder. The media stream downloaded to the media player may comprise audio, video, or any other desired type of media. In this manner, each media player can generate a decoder that differs, not only from the universal decoder, but may also differ from other media players thereby alleviating the burden on the media source from having to download the encoded media with a decoder specific to the target media player.

Abstract: A fast resume of a computer from a low power mode to a normal operating mode captures a power down message from the operating system of the computer to devices connected thereto. In response to the captured message, the device manager is instructed to remove the device from the operating system. The computer is powered down with the device removed. The system is later powered up with the device removed, allowing for faster resume to normal operation. After the computer has returned to normal operation, the device manager reinstates the removed device. The program to capture the power down message can be above the device driver in the driver stock or be an application running in the user mode of the operating system.

Abstract: A method for aligning consecutive scan lines of a mirror based visual system produced by the bi-directional scan of a resonant mirror is disclosed. The actual position for the mirror is determined or measured by any suitable method. The measured position of the mirror is used to generate a first trigger signal to start a scan line in a first direction at a selected location and to generate a trigger to start a scan line in the reverse direction at a second location.

Abstract: A method selects the data rate for pulse code modulation upstream transmission by determining an approximate transmit power before the upstream transmission reaches a transmit equalizer based on a recorder power output and a distance halfway between an outermost constellation point and a point following the outermost point. The determined approximate transmit power is multiplied by the power of the transmit equalizer to determine a post-equalizer transmit value. A data rate is selected which is less than a predetermined regulatory limit.

Abstract: An improved method is provided for performing register allocation in a compiler. This method determines the allocation of a plurality R of registers of a processor for use during the execution of a software program. The register allocation process is treated as a graph-coloring problem, such that an interference graph is constructed for the software program, the graph is simplified, and an R-coloring the interference graph to the extent possible is attempted. Then, spill code is inserted in the software program each for each uncolored node of the graph, a new interference graph is constructed, and the process is repeated. During the simplification process, nodes with degree greater than or equal to R are removed from the graph in an order dictated by a spill cost metric. During the coloring process, these same nodes are reinserted in the graph in an order dictated by reapplying the spill cost metric.

Abstract: Apparatus and methods for removing jitter and stabilizing the feed back system of a torsional hinged device with minimal changes to the system. The stabilization is accomplished by spatially isolating the pivoting mirror structure from all drive, support and packaging structures to reduce air drag. The mirror structures may be further stabilized by tailoring the drive mechanism and the position of the mechanism to produce substantially pure rotational drive torque on the mirror.

Abstract: According to one embodiment of the invention, a method for integrating low Schottky barrier metal source/drain includes providing a substrate, forming an epitaxial SiGe layer outwardly from the substrate, forming an epitaxial Si layer outwardly from the SiGe layer, and forming a metal source and a metal drain.

Abstract: Extended-drain MOS transistor devices and fabrication methods are provided, in which a drift region of a first conductivity type is formed between a drain of the first conductivity type and a channel. The drift region comprises first and second portions, the first portion extending partially under a gate structure between the channel and the second portion, and the second portion extending laterally between the first portion and the drain, wherein the first portion of the drift region has a concentration of first type dopants higher than the second portion.

Abstract: A memory system or a digital signal processor (DSP) includes single-bit-error detection hardware in its level two (L2) memory controller to mitigate the effects of soft errors. Error detection hardware detects erroneous data that is fetched by the central processing unit and signals the central processing unit. The parity is generated and checked only for whole memory line accesses. This technique is especially useful for cache memory. The central processing unit can query the memory controller as to the specific location that generated the error and decide the next course of action based on the type of data affected.

Abstract: A system comprising a processor adapted to activate multiple security levels for the system and a monitoring device coupled to the processor and employing security rules pertaining to the multiple security levels. The monitoring device restricts usage of the system if the processor activates the security levels in a sequence contrary to the security rules.

Abstract: A torsional hinged mirror assembly having a hinge plate having a central portion and a pair of torsional hinges extending outwardly in opposite directions from the central portion along a first axis and a first pair of support spines extending from the central portion in a second direction substantially perpendicular to the first axis. A mirror plate is attached to the hinge plate and has a reflecting side and a back side, a second pair of support spines located along a perimeter of the back side and extending generally in the second direction, wherein the first pair of support spines on the hinge plate and the second pair of support pines on the mirror plate are aligned and the back side of the mirror plate being attached to the hinge plate.

Abstract: A power supply has a plurality of switching regulators providing a like plurality of regulated output voltages. The oscillators of the switching regulators are synchronized with one another by a synchronization signal. A synchronization signal detector is provided on one or more of the switching regulators to shift the switching frequency of the oscillator to a lower frequency upon detection of a synchronization signal.

Abstract: A circuit for receiving multiple serial datastreams in parallel is disclosed. A bit clock is recovered from each data stream, there being one data bit for ach transition of the clock signal both positive and negative going. The phases of the bit clocks are compared and are adjusted by 180 degrees so that the positive going edges of all occur close to each other. The bits of each stream are assembled into words under the control of a word clock. In one embodiment a common word clock is derived form the set of bit clocks as a whole. In another embodiment each stream is provided with its own word clock which is aligned to positive edges of the respective bit clocks that are close to each other.

Abstract: Semiconductor devices and manufacturing methods therefor are disclosed, in which a drain-extended MOS transistor comprises a self-aligned floating region proximate one end of the transistor gate and doped with a first type dopant to reduce channel hot carrier degradation, as well as an oppositely doped first source/drain laterally spaced from the first end of the gate structure in a semiconductor body. The device may further comprise a resurf region doped to a lower concentration than the floating region to facilitate improved breakdown voltage performance. A method of fabricating a drain-extended MOS transistor in a semiconductor device is disclosed, comprising providing first dopants to a floating region in a semiconductor body, which is self-aligned with the first end of a gate structure, and providing second dopants to source/drains of the semiconductor body, wherein the first and second dopants are different.

Abstract: A digital system is provided with a secure mode (3rd level of privilege) built in a non-invasive way on a processor system that includes a processor core, instruction and data caches, a write buffer and a memory management unit. A secure execution mode is thus provided on a platform where the only trusted software is the code stored in ROM. In particular the OS is not trusted, all native applications are not trusted. A secure execution mode is provided that allows virtual addressing when a memory management unit (MMU) is enabled. The secure execution mode allows instruction and data cache to be enabled. A secure execution mode is provided that allows all the system interruptions to be unmasked. The secure mode is entered through a unique entry point. The secure execution mode can be dynamically entered and exited with full hardware assessment of the entry/exit conditions. A specific set of entry conditions is monitored that account for caches, write buffer and MMU being enabled.

Abstract: An amplifier includes a differential amplifier (10) having an input stage (20) for amplifying a differential input signal (Vin), and an output stage (6) coupled to the input stage (20) for producing and output signal (Vout). The input stage (20) includes main input circuitry (20A) for amplifying small-signal values of the input signal (Vin) and alternative input circuitry (20B) for amplifying the input signal (Vin) during conditions which cause thermal imbalance in the main input circuitry (20B). The input stage (20) includes switching circuitry (12) for coupling the input signal (Vin) to the main input circuitry (20A) during normal small-signal operating conditions and to the alternative input circuitry (20A) during large-signal operating conditions that cause thermal imbalance in the main input circuitry (20B).

Abstract: The operating range of joint additive and convolutive compensating method is extended by enhanced channel estimation procedure that adds SNR-dependent inertia and SNR-dependent limit on the channel estimate.

Abstract: When a RESET signal is generated in a target processor during a test procedure, a reset sync marker is generated in a program counter trace stream. The reset sync marker includes a plurality of packets, the packets identifying that the reset sync marker is the result of a RESET signal. The packets identify the program counter address at the time of the generation of the RESET signal and relate the reset sync marker to a timing trace stream. When the RESET signal is removed, a second (reset-off) sync marker is generated identifying the removal of the RESET signal, identifying the program counter address, and relating the second sync marker to the timing trance stream.