Abstract: An analog-to-digital converter device capable of measuring inputs beyond a supply voltage including: an N bit analog-to-digital converter powered by a supply voltage and a reference voltage; a range resolution stage capable of receiving inputs at higher voltages than the supply voltage, providing an input to the analog-to-digital converter, and outputting a logic value of one for the N+1th bit in response to an input signal higher than the reference voltage; and a bootstrapped input multiplexer stage for connecting low voltage input signals directly to the analog-to-digital converter and for connecting input signals that can exceed the supply voltage to the range resolution stage.

Abstract: An integrated preamplifier circuit for detecting a signal current from a photodiode and converting the signal current into an output voltage is provided. The circuit includes a signal amplifier and a dummy amplifier, the dummy amplifier being matched to the signal amplifier. Each of these amplifiers includes an input transistor and an output transistor, the input transistor of the signal amplifier receiving an input signal derived from the signal current and the input transistor of the dummy amplifier receiving no input signal. The signal and dummy amplifiers provide the desired differential output signal. The input transistors of the signal and dummy amplifiers each have a biasing current source forced to follow a reference current source implemented within the integrated circuit.

Abstract: A method (100) of fabricating an electronic device (200) formed on a semiconductor wafer. The method forms a layer (215) of a first material in a fixed position relative to the wafer. The first material has a dielectric constant less than 3.6. The method also forms a photoresist layer in (216) a fixed position relative to the layer of the first material. The method also forms at least one void (220) through the layer of the first material in response to the photoresist layer. Further, the method subjects (106) the semiconductor wafer to a plasma which incorporates a gas which includes hydrogen so as to remove the photoresist layer.

Abstract: According to one embodiment of the present invention, a method for color illumination for an image display system includes field sequentially operating an array of emitters to generate a sequence of light beams. Each light beam includes one color. A first light beam of a first color is combined with a second light beam of a second color. The first and second light beams are combined in an optical path to travel concurrently. The combination of the first and second light beams results in a composite color coordinate. The combination of the first and second light beams are directed at a spatial light modulator operable to receive the combination and produce a desired color on a display.

Abstract: A BARC or other sacrificial fill layer etch comprises a selective etch chemistry of Ar/O2/CO. The BARC etch may be used in a via-first dual damascene method. After via (116) pattern and etch, a BARC/sacrificial fill layer (120) is deposited to fill the via (116) and coat the IMD (110). The excess sacrificial fill layer (120) material over the IMD (110) is removed using the Ar/O2/CO etch. A trench resist pattern (125) is formed over the BARC layer (120). During the main trench etch, portions of sacrificial fill layer (120) remain in the via to protect the etch-stop (104) at the bottom of the via (116).

Abstract: This invention is a new CMOS voltage booster (20) having an output which can be used in memories to boost the word line voltage above VDD or other voltage boosting applications. The CMOS booster includes a NMOS FET (MN1) to charge a boosting capacitor (C1) to VDD at the end of each memory access and includes a PMOS FET (MP1, MP2) to keep the voltage at the output at VDD during standby. By using this combination, the word line rise time, the size of the booster, and the power consumption during access are significantly reduced. The gate of the NMOS FET (MN1) is boosted above VDD+Vthn by a small capacitor (C2) to charge the word line boosting capacitor to VDD at the end of each memory access. The small capacitor (C2) is pre-charged to VDD by a NMOSFET (MN2) whose gate is connected to the word line boosting capacitor. The gate of each PMOS FET (MP1, MP2) is shorted to its source to turn if off during boostenig. Transistor (MP3) facilitates boosting the NMOS FET (MN1) above VDD.

Abstract: The present invention provides a method for implanting a dopant in a substrate and a method for manufacturing a semiconductor device. The method for implanting a dopant, among other steps, including tilting a substrate (310) located on or over an implant platen (305) about an axis in a first direction with respect to an implant source (320) and implanting a portion of an implant dose within the substrate (310) tilted in the first direction. The method further includes tilting the substrate (310) having already been tilted in the first direction about the axis in a second opposite direction, and implanting at least a portion of the implant dose within the substrate (310) tilted in the second opposite direction.

Abstract: The present invention provides, in one aspect, a method of designing an integrated circuit. In this particular aspect, the method comprises reducing soft error risk in an integrated circuit by locating a structure, relative to a node of the integrated circuit to reduce a linear energy transfer associated with a sub-atomic particle, into the node, such that the linear energy transfer does not exceed a threshold value associated with the integrated circuit.

Abstract: System and method for operating four resonant torsional hinged mirrors such as torsional hinged MEMS devices at the same oscillating frequency suitable for use in a color printer requiring four serially arranged line printers.

Abstract: A device with a solder joint made of a copper contact pad (210) of certain area (202) and an alloy layer (301) metallurgically attached to the copper pad across the pad area. The alloy layer contains copper/tin alloys, which include Cu6Sn5 intermetallic compound, and nickel/copper/tin alloys, which include (Ni,Cu)6Sn5 intermetallic compound. A solder element (308) including tin is metallurgically attached to the alloy layer across the pad area. No fraction of the original thin nickel layer is left after the reflow process. Copper/tin alloys help to improve the drop test performance, nickel/copper/tin alloys help to improve the life test performance.

Abstract: A high speed parser containing a content addressable memory (CAM) providing select values to multiplexers. The CAM is programmed to implement search rules which examine input data for specific semantics according to a protocol, and outputs the specific bit positions at which the corresponding desired data units are present. The outputs are provided to multiplexers to cause the desired data units to be selected on the corresponding output paths of the multiplexors.

Abstract: A differential input comparator circuit comprises an input stage comprising dual polarity input voltages and an output stage adapted to output a differential voltage based on the input voltages, wherein the differential voltage is adapted to be transmitted to a comparator and wherein the circuit has high input impedance and works with high input voltage swings.

Abstract: A circuit for receiving multiple serial datastreams in parallel is disclosed. A bit clock is recovered from each data stream, there being one data bit for each transition of the clock signal both positive and negative going. The phases of the bit clocks are compared and are adjusted by 180 degrees so that the positive going edges of all occur close to each other. The bits of each stream are assembled into words under the control of a word clock. In one embodiment a common word clock is derived form the set of bit clocks as a whole. In another embodiment each stream is provided with its own word clock which is aligned to positive edges of the respective bit clocks that are close to each other.

Abstract: A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a memory operation initiation signal in response thereto, while the memory control circuit is operable to receive the memory operation initiation signal and generate one or more control signals to initiate a memory operation in response thereto. The memory control circuit is further operable to identify completion of the memory operation and generate a cycle ready strobe signal in response thereto. The memory input circuit receives the cycle ready strobe signal as an input and generates a next memory operation initiation signal in response thereto for initiation of a next memory operation.

Abstract: A dielectric layer (50) is formed over a semiconductor (10) that contains a first region (20) and a second region (30). A polysilicon layer is formed over the dielectric layer (50) and over the first region (20) and the second region (30). The polysilicon layer can comprise 0 to 50 atomic percent of germanium. A metal layer is formed over the polysilicon layer and one of the regions and reacted with the underlying polysilicon layer to form a metal silicide or a metal germano silicide. The polysilicon and metal silicide or germano silicide regions are etched to form transistor gate regions (60) and (90) respectively. If desired a cladding layer (100) can be formed above the metal gate structures.

Abstract: A display system includes a light source 110 and a spatial light modulator 122 located to receive light from the light source. The spatial light modulator (e.g., a DMD) includes a number of independently controllable elements that are activated for a period of time to display light of a desired brightness. A light sensor 136 is located to determine a characteristic of light from the light source 110. A control circuit 126 is coupled to the spatial light modulator 122 and controls the period of time that the independently controllable elements are activated. This period of time is based at least in part by an input received from the light sensor 136.

Abstract: A system for detecting liquid flow from a nozzle in a semiconductor processing device includes a first fiber optic sensor, a second fiber optic sensor, and an amp. The first fiber optic sensor and second fiber optic sensor are located on opposite sides of at least one nozzle. The first fiber optic sensor transmits light, and the second fiber optic sensor receives more of the light when the nozzle is not dispensing liquid than when the nozzle is dispensing liquid. The amp is coupled to the first fiber optic sensor and second fiber optic sensor. The amp indicates whether the nozzle is dispensing liquid according to an amount of the light received at the second fiber optic sensor.

Abstract: A wireless device in a wireless network transmits a data frame even in the presence of in-band interference (from transmission of other devices) on a shared channel provided in the wireless network. In an embodiment, configuration data is provided to the wireless device indicating whether frames be transmitted (stomped) or not in the presence of such inband interference. If the configuration data indicates that the wireless device transmit in the presence of in-band interference, the wireless device transmits a frame if the transmitter of the interfering communication is determined to be from a different basic service set (BSS).

Abstract: A transmit channel (gt1, h, gr2) through which a first wireless communication transceiver is to transmit to a second wireless communication transceiver can be estimated using information indicative of a relationship between the transmit channel and a receive channel (gt2, h, gr1) through which the first wireless communication transceiver receives communications from the second wireless communication transceiver. The relationship information (35) is combined (37) with further information (31) to produce an estimate of the transmit channel.

Abstract: A nonvolatile memory array is encased in a P-well, and the P-well encased in a deep N-well, the two wells separating the memory array from the integrated circuit substrate and from the other circuitry of the integrated circuit. At the same time the deep N-well is formed for the nonvolatile memory array, deep N-wells are formed for the high-voltage P-channel transistors of the logic circuitry. At the same time the P-well is formed for the nonvolatile memory array, P-wells are formed for the low-voltage N-channel transistors. The memory array contains nonvolatile cells of the type used in the ultra-violet-erasable EPROMs. During erasure, the isolated-well formation allows the source, the drain and the channel of selected cells to be driven to a positive voltage. The isolated well is also driven to a positive voltage equal to, or slightly greater than, the positive voltage applied to the source and drain, thus eliminating the field-plate breakdown-voltage problem.