Abstract: Integrated circuit die on wafer are electronically selected for testing using circuitry (161, 201, PA1–PA4) provided on the wafer.

Abstract: A voltage generation circuit generates a reference voltage using a bandgap reference. A countering circuit is included to adaptively counter for any deviations caused in a bandgap reference voltage such that the reference voltage is independent of fabrication process variations and changes in ambient temperature. In an embodiment, current, proportionate to deviation in absolute value of Vbe from a nominal value, is injected into an emitter-base junction to cause Vbe to equal the nominal value.

Abstract: A method for manufacturing an integrated circuit 10 having transistors 20, 30 of two threshold voltages where protected transistor stacks 270 have a gate protection layer 220 that are formed with the use of a single additional mask step. Also, an integrated circuit 10 having at least one polysilicon gate transistor 20 and at least one FUSI metal gate transistor 30.

Abstract: The present invention provides a method of forming a dual work function metal gate microelectronics device 200. In one aspect, the method includes forming nMOS and pMOS stacked gate structures 315a and 315b. The nMOS and pMOS stacked gate structures 315a and 315b each comprise a gate dielectric 205, a first metal layer, 305 located over the gate dielectric 205 and a sacrificial gate layer 310 located over the first metal layer 305. The method further includes removing the sacrificial gate layer 310 in at least one of the nMOS or pMOS stacked gate structures, thereby forming a gate opening 825 and modifying the first metal layer 305 within the gate opening 825 to form a gate electrode with a desired work function.

Abstract: A pressure-measuring glow plug for a diesel engine with a plug body (3, 4) for insertion into a cylinder of the diesel engine, a heating rod (1) which is arranged in the plug body (3, 4), and a pressure sensor, which is arranged under an initial tension between the heating rod (1) and the plug body (3, 4), in such a way that the pressure sensor (7) is acted upon by the pressure prevailing in the combustion chamber of the cylinder. The heating rod (1) transmits the pressure in the combustion chamber of the cylinder to the pressure sensor (7) and is arranged so as to be displaceable in a sliding manner in the axial direction relative to the plug body (3, 4). A seal in the form of a bellows-shaped component (2) is provided between the heating rod (1) and the plug body (3, 4).

Abstract: A driver circuit includes a first transistor coupled between an input supply node and an output node. The first transistor operates in one of a conductive state to couple the output node with the input supply node and non-conductive state according to cooperative operation of a second transistor and a third transistor. The second transistor is coupled to provide a control input to drive the first transistor to the conductive state thereof in response a first input signal provided at a control input of the second transistor. The third transistor is coupled to provide an output at the output node in response to a second input signal provided at a control input of the third transistor, the first and second input signals being out of phase with each other. Circuitry is coupled between the input supply node and the control input of the first transistor to provide reduced impedance at the control input of the first transistor according to operation of the second transistor.

Abstract: A process initializes the state of an output memory circuit of a scan cell located at the boundary of a logic circuit within an integrated circuit. Data is scanned into an input memory circuit of the cell while maintaining the cell in a mode providing normal operation of the logic circuit. The cell is placed in a test mode that disables normal operation of the logic circuit. The data scanned into the input memory circuit is transferred into the output memory circuit simultaneous with the placing the cell in the test mode. A transmission gate between the logic circuit and the output memory circuit and a transmission gate between the input memory circuit and the output memory circuit effect the changes between normal operation and test modes.

Abstract: The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes forming a gate structure (130) over a substrate (110), the gate structure (130) having L-shaped sidewall spacers (430) on opposing sidewalls thereof and placing source/drain implants (310 or 510) into the substrate (110) proximate the gate structure (130). The method for manufacturing the semiconductor device further includes removing at least a portion of a horizontal segment of the L-shaped sidewall spacers (430).

Abstract: An embodiment of the invention is a method of cleaning a material stack 2 that has a hard mask top layer 8. The method involves cleaning the material stack 2 with a fluorine-based plasma etch. The method further involves rinsing the material stack 2 with a wet clean process.

Abstract: A packaged micromechanical device (100) having a blocking material (116) encapsulating debris-generating regions thereof. The blocking material (116) prevents the generation of debris that could interfere with the operation of the micromechanical device (100). Debris-generating regions of the device (100), including debris-creating sidewalls and any debris-harboring cavities, as well as electrical connections (108) linking the device (100) to the package substrate (102) are encapsulated by the blocking material (116). The blocking material (116) avoids contact with any debris-intolerant regions (118) of the device (100). A package lid (124), which is glass in the case of many DMD packages, seals the device (100) in a package cavity (120).

Abstract: An amplifier system can include a biasing amplifier that provides a first amplified signal to a DC blocking element that is connected with a load based on a first control signal. A power amplifier provides a second amplified signal for driving the load based on a second control signal. A control system controls the biasing amplifier to charge the DC blocking element so as to mitigate a voltage drop across the load (e.g., to substantially eliminate audible artifacts) when the power amplifier is activated to provide the second amplified signal.

Abstract: A sequential color filter and display system. The sequential color filter comprising: a set of at least three color filters (102). The color filters can be arranged in a cylindrical configuration and may have a cooling fan (506) attached. The set of color filters typically comprises a red filter, a green filter, and a blue filter, and can comprise a red filter, a green filter, a blue filter, and a clear filter. A motor may be connected to the set of color filters for rotating the set of color filters and the cooling fan about a common axis. The color filters may be arranged in a spiral configuration when a cylindrical sequential color filter is provided. The preceding abstract is submitted with the understanding that it only will be used to assist in determining, from a cursory inspection, the nature and gist of the technical disclosure as described in 37 C.F.R. § 1.72(b). In no case should this abstract be used for interpreting the scope of any patent claims.

Abstract: An amplifier circuit includes an amplifier section (700), an equalization section (770), and an activation section (720). The P-channel transistors (702, 704) of the amplifier section are coupled to a supply terminal (802). The N-channel transistors (706, 708) of the amplifier section are coupled between the P-channel transistors and the first and second input terminals (760, 762), respectively. In the activation section, first and second pull down transistors (722, 724) are coupled between the first and second input terminals, respectively, and a second power supply terminal (726), and third pull down transistor between the first and second input terminals. The control gates of the first, second and third pull down transistors are coupled to each other. In operation, a voltage signal applied to the first and second input terminals is amplified by the N-channel transistors. A control signal is then applied to couple the first and second input terminals to a supply voltage.

Abstract: The addition of DMD illumination modulator(s) 702 in series with projection SLM(s) 706/709 to produce high-performance projection displays with improved optical efficiency, reliability, and lower maintenance requirements. This approach eliminates the vibration, audible noise, and safety problems associated with high speed rotating color filter wheels 203 commonly used in SLM projectors and controls the light applied to individual areas of the projection SLM(s).

Abstract: A system and method are provided that are operable for network communications that promote network devices to receive a transmit request, transmit a first part of a frame by a physical layer without a second part of the frame from a medium access control layer, and request the second part of the frame by the physical layer from the medium access control layer. These systems and methods also allow, in some embodiments, for the transmitting of the second part of the frame by the physical layer with data from the medium access control layer.

Abstract: An integrated stacked capacitor comprises a first capacitor film (46) of polycrystalline silicide (poly), a second capacitor film (48) and a first dielectric (26) sandwiched between the first capacitor film (46) and second capacitor film (48). A second dielectric (34) and a third capacitor film (50) are provided. The second dielectric (34) is sandwiched between the second capacitor film (48) and third capacitor film (50). A method for fabrication of an integrated stacked capacitor comprises the following sequence of steps: applying a polysilicide layer (20) to form the first capacitor film (46); applying a first dielectric (26); applying a first metallization layer (28) to form the second capacitor film (48); applying a second dielectric (34); and applying a second metallization layer (34) to form the third capacitor film (50).

Abstract: A method and system in which a semiconductor wafer having a plurality of dies is inspected through a visual inspection and/or an electrical test. If certain of the dies on the wafer pass the inspection, then windows are mounted or affixed above those certain dies while they are still a part of the wafer.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and a method for manufacturing an integrated circuit. The semiconductor device (100), among other possible elements, includes a first transistor (120) located over a semiconductor substrate (110), wherein the first transistor (120) has a metal gate electrode (135) having a work function, and a second transistor (160) located over the semiconductor substrate (110) and proximate the first transistor (120), wherein the second transistor (160) has a plasma altered metal gate electrode (175) having a different work function.

Abstract: Semiconductor devices formed on wafers are inspected using a master wafer. A subject wafer of a semiconductor design is provided. The subject wafer has dies wherein semiconductor devices of the semiconductor design are formed and at a stage of fabrication. A current layer of the subject wafer is scanned to obtain a scanned layer/image. A master wafer comprising individual wafer/layer maps is obtained. The scanned layer is compared with a corresponding layer map. Matching and non-matching defects are identified from repetitive defects within the corresponding layer map and defects within the scanned layer. The matching defects are reviewed to classify and or identify causality. The master wafer is then updated.

Abstract: Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure (106, 306, 400, 404) and the required current density throughput of an electrical contact structure (108, 308, 402, 406) are determined. A required electrical contact area is determined based on the required current density, and the electrical contact structure is then designed to minimize the required electrical contact area with respect to the emitter structure area.