Abstract: A separated synchronizing scrambler/descrambler pair that removes the possibility of catastrophic error due to improper transmission of initial condition information without disrupting the OFDM modulation scheme of a system that includes error-correction coding circuitry and replay variation. A transmitting device within the pair includes a first and a second data scrambler wherein the first data scrambler couples to receive the incoming data stream and filters the incoming data stream to provide a first filtered signal using a key signal. The second data scrambler, having an initial condition, couples to receive the first filtered signal and converts it into a scrambled signal using a scrambling seed. The second data scrambler comprises a random series generator for generating the scrambling seed to convert the first filtered signal into a scrambled signal. The scrambled signal is transmitted to the receiving device.

Abstract: Semiconductor devices (102) and fabrication methods (10) are provided, in which a nitride film (130) is formed over NMOS transistors to impart a tensile stress in all or a portion of the NMOS transistor to improve carrier mobility. The nitride layer (130) is initially deposited over the transistors at low temperature with high hydrogen content to provide a moderate tensile stress in the semiconductor body prior to back-end processing. Subsequent back-end thermal processing reduces the film hydrogen content and causes an increase in the applied tensile stress.

Abstract: A system and method are implemented for preventing regulated supply undershoot in state retained latches of a leakage controlled system, using a voltage source depending on a reference voltage that includes a decay to resolve undesirable undershoot.

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. A first oxide layer is formed in core and I/O regions of a semiconductor device (506). The first oxide layer is removed (508) from the core region of the device. A high-k dielectric layer is formed (510) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions of the core and I/O regions. A second oxide layer is formed (516) within NMOS regions of the core and I/O regions and a nitridation process is performed (518) that nitrides the second oxide layer and the high-k dielectric layer.

Abstract: One embodiment of the invention is a method for evaluating a material such as low-k dielectric, by a stress-generating test tool such as a needle. The evaluation object is shaped as a stack of adhering layers: low-k dielectric, first metal (preferably copper), barrier metal (preferably tantalum nitride), and second metal (preferably aluminum). A numerical correlation is established between a cracking in the barrier metal layer caused by probing and a damage in the layer of insulating material-to-be-tested. A predetermined number of locations of the top metal layer is selected for the probing step comprising touch-down, applying force, and lifting is repeated so that the number of repeats provide a pre-determined statistical confidence level.

Abstract: The present invention provides a complementary metal oxide semiconductor (CMOS) device, a method of manufacture therefor, and an integrated circuit including the same. The CMOS device (100), in an exemplary embodiment of the present invention, includes a p-channel metal oxide semiconductor (PMOS) device (120) having a first gate dielectric layer (133) and a first gate electrode layer (138) located over a substrate (110), wherein the first gate dielectric layer (133) has an amount of nitrogen located therein. In addition to the PMOS device (120), the CMOS device further includes an n-channel metal oxide semiconductor (NMOS) device (160) having a second gate dielectric layer (173) and a second gate electrode layer (178) located over the substrate (110), wherein the second gate dielectric layer (173) has a different amount of nitrogen located therein. Accordingly, the present invention allows for the individual tuning of the threshold voltages for the PMOS device (120) and the NMOS device (160).

Abstract: Processes for the removal of a layer or region from a workpiece material by contact with a process gas in the manufacture of a microstructure are enhanced by the ability to accurately determine the endpoint of the removal step. A vapor phase etchant is used to remove a material that has been deposited on a substrate, with or without other deposited structure thereon. By creating an impedance at the exit of an etching chamber (or downstream thereof), as the vapor phase etchant passes from the etching chamber, a gaseous product of the etching reaction is monitored; and the endpoint of the removal process can be determined.

Abstract: A wireless device for routing data in a mesh network is provided. The device includes a component operable to promote routing in the mesh network according programmable parameters. The wireless device includes a transmitter operable to promote communications with at least one other device in the mesh network.

Abstract: Disclosed above are various embodiments of VoIP communication systems that utilize low cost IP phones that rely on a centralized VoIP controller for much of the processing. Reducing the processing taking place on an IP phone may reduce the number of components that need to be on the IP phone which may result in a less expensive IP phone in terms of both cost and power. When the IP phone is embodied as a WIPP, the reduced processing may also result in more efficient communication between the WIPP and an AP. The increased communication efficiency may result in less power being used by the WIPP and effectively extend the battery life. Since a number of redundant components have been centralized, the VoIP system as a whole may be less costly. Also, centralized control may provide greater functionality and versatility in the setup and configuration of a VoIP communication system.

Abstract: The present invention provides a method for testing an electrical property of one or more functionally separate transistors located within an active region that is common with other transistors, a method for characterizing the leakage current of at least one of a plurality of functionally separate transistors located in a common active region of a circuit, and a test structure for testing one or more functionally separate transistors located within a common active region. The method for testing the electrical property, among other steps, includes providing a pair of functionally separate transistors (110) located within a common active region, and biasing a terminal (135) between the pair (110) relative to gates (125, 155) of the pair (110) and terminals (130, 160) outlying the pair (110) to obtain a leakage current associated with the pair (110).

Abstract: Increasing the input common-mode range of a circuit which accepts differential signals as inputs. Such an increase may be attained by correcting an input signal at continuous levels or at 2 or more discrete levels) without changing the strength represented by the input signal. In an embodiment, the common-mode component of an input signal is measured, and a correction voltage proportional to the difference between the measured common-mode component and a reference voltage, is generated. The correction voltage is coupled to the input terminals of the differential circuit to correct for any deviations from a desired level of common-mode voltage at the input terminals of the differential circuit. The approaches are applied to a switched-capacitor differential amplifier used in a sample-and-hold portion of an ADC.

Abstract: In accordance with the present invention, a system and method to increase die stand-off height in a flip chip are provided. The system includes a plurality of separator pedestals disposed between a first face of a die and a second face of a substrate, the substrate positioned generally parallel with, and spaced apart from, the die, and the first face being opposite the second face. The plurality of separator pedestals are operable to selectively force the die and substrate apart, increasing the stand-off height of the flip chip assembly.

Abstract: A wireless network is disclosed in which individual wireless stations can be configured to implement any of a plurality of physical configurations including antenna configurations. Such antenna configurations may include, without limitation, multiple input multiple output (MIMO) and single input single output (SISO). Different types of MIMO configurations can also be implemented such as open loop MIMO and closed loop MIMO.

Abstract: A method for estimating carrier frequency offset (CFO) and sampling frequency offset (SFO) in an Orthogonal Frequency Division Multiplexing (OFDM) system having a plurality of pilot tones. The absolute phase angle for each pilot tone is measured, and estimates of the CFO and the SFO are derived using a weighted least-squares methodology. More particularly, the phase of each pilot tone is measured for a number (n) of symbol times; for each of the pilot tones, the slope of a phase angle change from symbol time to symbol time is estimated using a best least-squares fit of the measured phases to a straight line; and a weighted least-squares best-fit straight line is determined to find an estimated phase angle differential value (?(i)) for each pilot tone; wherein a slope of the best-fit straight line yields an estimate of the SFO, and an intercept with the best-fit straight line yields an estimate of the CFO.

Abstract: When a NEW SECONDARY CODE EXECUTION START POINT signal is generated in a target processor during a test procedure after the return from an interrupt service routine (i.e., an original secondary code sequence), a sync marker is generated in a program counter trace stream. The sync marker includes a plurality of packets, the packets identifying that the sync marker is has been generated as a result of the NEW SECONDARY CODE EXECUTION START POINT signal. The new secondary program code start point sync marker identifies the absolute program counter address at the time of the generation of the NEW SECONDARY CODE EXECUTION START POINT signal and relates the NEW SECONDARY CODE EXECUTION START POINT signal sync marker to a timing trace stream.

Abstract: A single-inductor dual-output buck converter facilitates power conversion by converting a single DC power source/supply into two separate DC outputs, each of which can be configured to provide a selected/desired voltage. The converter includes a single inductor and three power switches, which control operation of the converter. The converter has four basic stages of operation in which power is initially supplied to a first output that also stores charge. Subsequently, the stored charge of the first output is employed to provide power to a second output.

Abstract: This invention detects a stall in a stepper motor by determining a motor winding current for each stepper pulse and determining if the winding current of a particular stepper pulse meets predetermined criteria. The motor winding current may be determined by measuring a voltage across an ON field effect transistor during a stepper pulse and calculating a winding current using an assumed ON field effect transistor resistance. The predetermined criteria may by a calculated motor winding current greater than a predetermined threshold, greater than prior pulse by more than a predetermined threshold or greater than a prior pulse by more than a predetermined factor.

Abstract: An efficient way to generate the address sequence for the RAM implementation of Forney's (P, D, m) interleavers requires only A+1+2P memory locations, which is close to the theoretical minimum. Here A is the average delay of the symbols through the interleaver. The address generation circuit (with simple adders and registers) works for variable P,D,m. This is achieved by decomposing the (P,D,m) interleaver into a concatenation of a multiplexed interleaver (implemented with A+1 memory locations), followed by a block interleaver (implemented with 2P memory locations). In many applications, these 2P memory locations can be treated as part of the memory for controlling the data flow of the system.

Abstract: A high voltage level shifter having a cost effective design that saves chip architecture and power. The high voltage level-shifter includes a resistor connected between a first node and a first power supply rail. An inverter couples to receive an input signal to provide an inverted input signal. A first circuit portion couples to receive the inverted input signal and connects between the first power supply rail and a second power supply rail for converting a high voltage signal into a low voltage signal. The first circuit portion includes a first clamp circuit, wherein the first circuit portion is biased through the first clamp circuit and the first node. A second circuit portion couples to receive the input signal and connects between the first power supply rail and a second power supply rail for converting a low voltage signal into a high voltage signal.

Abstract: The present invention provides a system, method, and apparatus for providing improved quality of service in a wireless local area network transmission system, the network comprising at least two devices, the quality of services defined at least in part by data communicated by a first of the devices to other devices in the network through one or more quality of service parameters. In accordance with the present invention, a change indicator is initialized at the start of a monitoring period. Then, during the monitoring period, the stored parameters are monitored for changes in those of thee stored parameters that define the quality of service. When a change is detected, the change indicator is updated in response and other devices in the network are periodically notified of the current value of the change indicator. The other devices are operable to update locally stored quality of service parameters in response to detecting a change in the change indicator.