Abstract: A method and circuit (10) for achieving a fast EPR4 equalization start-up for an FIR filter (14) in a magnetic recording read channel is presented in which a three-level adaptation in an LMS coefficient equalizer (34) at an FIR output (16) is performed to provide a rough estimate of coefficients to said FIR filter (14). A 1+D operation (20) on the FIR output (16) is performed to generate an indirect mode EPR4 equalized signal (26), which may be applied to an input of a detector (32) of the read channel. After a predetermined time, the EPR4 equalized signal (30) is used to perform a five-level adaptation in the LMS coefficient equalizer (34) to provide a fine estimate of coefficients to said FIR filter (14). The method utilizes the robustness of a three-level PR4-target LMS adaptation of the EPR4 read channel in order to establish an initial setting of the coefficients of a newly-built system, which does not have very well known channel characteristics.

Abstract: A voltage regulator is provided for taking an input voltage and providing a multiple of output voltages of differing voltage values. The voltage regulator includes a power switch and an inductor for providing inductor current to various output nodes. Control switches and a decision logic block are used to regulate the flow of inductor current to the output nodes, in accordance with predetermined values stored in the decision logic block. In one exemplary arrangement, the voltage regulator may provide a multiple of positive and negative voltage outputs. In another arrangement, the voltage regulator may provide a multiple of positive or negative voltage outputs or both.

Abstract: A method of compensating for nonuniformities in an image sensor includes: providing an image sensing device 20; measuring test pixel signals from the image sensing device 20 during a test mode; determining which test pixel signals are greater than a fixed threshold level ST; and calculating nonuniformity coefficients for the pixels having test pixel signals greater than the fixed threshold level ST.

Abstract: A method for writing servo patterns on a hard disk drive disk in a hard disk drive assembly. The assembly includes a disk having at least one magnetic surface in which a reference pattern has been written, determining a reference track. Also included is an actuator having a shaft engaged with the disk to provide rotational motion to the disk, an actuator arm, and a micro-actuated read/write head mounted on the actuator arm. The method includes the following steps. First, the read/write head is used to position the actuator arm at a first fixed position over the reference track. The actuator arm is maintained at the first fixed position while the read/write head is used to write a second servo pattern, determining a second track. The read/write head is used to position the actuator arm at a second fixed position over the second track. Then, the actuator arm is maintained at the second fixed position while the read/write head is used to write a third servo pattern.

Abstract: A group of client calculators (18) communicates by determining whether a aster calculator (14) is a member of the group. If the master calculator (14) is present, the client calculators (18) determine whether the master calculator (14) has allowed communication between the client calculators (14). The client calculators may communicate if the master calculator (14) is not present or if the master calculator (14) is present and has allowed communications between other of the client calculators (18).

Abstract: A leadframe for use with integrated circuit chips, comprising a leadframe base made of aluminum or aluminum alloy having a surface layer of zinc; a first layer of nickel on said zinc layer, said first nickel layer deposited to be compatible with aluminum and zinc; a layer of an alloy of nickel and a noble metal on said first nickel layer; a second layer of nickel on said alloy layer, said second nickel layer deposited to be suitable for lead bending and solder attachment; and an outermost layer of noble metal, whereby said leadframe is suitable for solder attachment to other parts, for wire bonding, and for corrosion protection.

Abstract: A recognition switch assembly (10) has a movable contact assembly (24) mounted on an actuator (22) mounted for sliding movement along a longitudinal direction (12a) in a housing (20) with a stationary contact board (26) mounted on the housing over the movable contact assembly (24). The actuator is formed with a laterally deflectable beam (22q) on one side of the actuator having a protrusion (22s) which cooperates with space protrusions (22p) on the opposed side for sliding engagement with opposed sidewalls (20f, 20g) of the housing. A pair of vertically deflectable beams (22k) having a protrusion (22n) slidingly engage platform surfaces (20b, 20c). When mounted in the housing, the beams are deformed to eliminate clearances between the actuator (22) and the housing (20) in both the vertical and lateral directions resulting in an improved, vibration independent, electrical output signal of the switch assembly.

Abstract: Plural scan test paths (401) are provided to reduce power consumed during testing such as combinational logic (101). A state machine (408) operates according to plural shift states (500) to control each scan path in capturing data from response outputs of the combinational logic and then shifting one bit at a time to reduce the capacitive and constant state power consumed by shifting the scan paths.

Abstract: A PC card and corresponding WLAN system having an improved DAC operable at higher speed than heretofore achievable which exploits the sigma-delta principle in a different way. More particularly, the invention comprises a PC card (302) and corresponding WLAN system (300) that implement a digital-to-analog conversion circuit (105) including a storage means (110), such as a read only memory, for storing delta-sigma analog sequences corresponding to all possible values of a digital input (106) coupled to a plurality of one-bit digital to analog converters (120, 122, 124, 126). Each of the digital-to-analog converters (120, 122, 124, 126) are clocked by multi-phase clocks, such that each phase applied to each one of the digital-to-analog converters (120, 122, 124, 126) is delayed with respect to one another by the oversampling period.

Abstract: An electrical connection web, operable at high frequency and configured on a dielectric substrate, comprising a plurality of generally parallel signal lines having graduated width and variable spacings, and said widths and spacings cooperatively selected such that the characteristic impedance of said signal lines is approximately the same for each line of said plurality and approximately constant over the length of each said signal line, whereby signal integrity for each said line is enhanced and cross talk between said lines is reduced.

Abstract: A background offset cancellation technique based on interleaved auto-zero (IAZ) architecture for flash ADCs, moves the reference tap values up and down to accommodate auto-zeroing of differential comparators rather than switching the differential comparator reference point between two distinct reference taps. The technique eliminates a large number of complementary switches necessary to provide the reference tap values leading to substantial savings in area and power, and provides for improved settling characteristics of the reference ladder.

Abstract: An improved dynamic element matching technique for providing noise-shaping of non-linearity in data converters, such as a multi-bit digital-to-analog converter, is provided. The improved DEM technique is configured with a new method for generating the bit patterns, which permits a less complex digital DEM circuit that provides improved performance. The proposed DEM algorithm introduces a new priority calculation method in which a multi-bit quantizer can be used in an oversampled delta sigma modulator to produce an output which is converted to an output code, such as a thermometer code output. The thermometer code output can be coupled as input bits through a dynamic element matching sort block to provide an output comprising a plurality of bits. Each output bit of the dynamic element matching sort block is sampled and coupled back to each of a plurality of corresponding filters, which comprise cascaded integrators.

Abstract: The present invention relates to a high speed sample and hold circuit which comprises a plurality of sample and hold subcircuits coupled in parallel between an input and an output. The circuit also comprises a calibration circuit coupled to the plurality of sample and hold subcircuits. The calibration circuit is operable to establish a timing relationship between a hold signal and a clock signal for each of the plurality of sample and hold subcircuits which is generally the same. The established timing relationship reduces a timing mismatch between the plurality of sample and hold subcircuits and distortion associated therewith. The present invention also comprises a method of reducing timing mismatch in a high speed, parallel coupled sample and hold circuit.

Abstract: A method for manufacturing a semiconductor device includes forming a collector region of a semiconductor substrate and forming an isolation structure adjacent at least a portion of the collector region. The method also includes forming a gate stack layer adjacent at least a portion of the isolation structure and forming a base region of the semiconductor substrate adjacent at least a portion of the collector region. The base region comprises a base link up region proximate a lateral edge of the base region. A diffusion source layer is formed adjacent at least a portion of the base link up region. The method includes removing a portion of the gate stack layer to form a base electrode adjacent a portion of the base region and a gate electrode spaced apart from the base electrode. The gate electrode is located at a complementary metal oxide semiconductor (CMOS) area of the semiconductor device.

Abstract: A robust, low inductance electronic package for small area semiconductor chips is provided which includes a flexible polymer film having electronic circuitry on one or more major surfaces, a bumped flip chip integrated circuit attached to the first surface, an array of solder balls to the second surface, and the device encapsulated in a plastic molding compound. An assembly and packaging method is disclosed wherein multiple devices are encapsulated simultaneously on a continuous polymer film, thereby providing a method compatible with high volume and low cost manufacturing processes and equipment.

Abstract: In a digital amplifier of the PCM-UPWM type there is no negative feedback stage, which means that noise caused by the switching output stage of such an amplifier directly affects the audio signal. A regulation loop is inserted between the output and the input of the digital amplifier, the regulation loop being adapted to form a compensation signal c(k) which is multiplied by the audio signal to compensate noise and errors from the switching output stage.

Abstract: The failure rate of an integrated circuit (IC) is quickly determined by analyzing the corresponding design. The IC is partitioned into multiple cells, with each cell typically containing a logic gate. A default input signal is assumed for each cell and the default failure in time (FIT) rates of the cells are computed. The default signal is selected based on pessimistic assumptions on overshoots. The IC is analyzed to determine the cells (“overshoot cells”) that would actually experience overshoots. Detailed analysis is performed on the overshoot cells to determine exact FIT rates. The failure rate of the IC is determined based on the exact FIT rates for the overshoot cells and the default FIT rates for the remaining cells.

Abstract: A client-side modem (20) having capability of improved data rate upstream communications via a codec (2) in a central office (CO) to an Internet service provider (ISP) (10) is disclosed. The disclosed modem (20) includes a digital signal processor (DSP) (14) that, for upstream communications, performs a bit mapping function (22) upon the digital data so that the digital words are mapped to slicing levels of analog-to-digital conversion circuitry (A/D) (6) in the central office codec (2); in addition, bit mapping function (22) preferably maps the digital signal into symbols having fewer bits each than the maximum defined by the number of slicing levels of the A/D (6). A pre-equalize filter function (26) applies an approximate inverse channel response filter (as measured during the training process) to the bit mapped digital data, to maximize the transmitted data rage over the dispersive analog subscriber loop (ASL), with consideration for an average transmit power maximum specification.

Abstract: A buried channel PMOS transistor for analog applications is integrated into a digital CMOS process. A third well region (105) is formed by implanting a region in the semiconductor substrate with all the n-type and p-type implants used to form the n-well and p-well regions for the digital CMOS process. A gate dielectric layer (50) and gate layer (109) are formed above the third well (105) and comprise the gate stack of the buried channel PMOS transistor. The implants used to form the drain extension regions and the source and drain regions of the CMOS transistors are used to complete the buried channel PMOS transistor.

Abstract: A wireless base station having an improved DAC operable at higher speed than heretofore achievable which exploits the sigma-delta principle in a different way. More particularly, the invention comprises a base station 300 that implement a digital-to-analog conversion circuit (105) including a storage means (110), such as a read only memory, for storing delta-sigma analog sequences corresponding to all possible values of a digital input (106) coupled to a plurality of one-bit digital to analog converters (120, 122, 124, 126). Each of the digital-to-analog converters (120, 122, 124, 126) are clocked by multi-phase clocks, such that each phase applied to each one of the digital-to-analog converters (120, 122, 124, 126) is delayed with respect to one another by the oversampling period. An summer is coupled to each digital-to-analog converter (120, 122, 124, 126) for summing each output from each digital-to-analog converter (120, 122, 124, 126) to generate an analog output.