Abstract: The invention is a method for attaching an electronic component (40) having Ball Grid Array contacts (36) to a circuit board contact array (31) to prevent the solder balls (36) of the Ball Grid Array from fracturing and distorting during solder reflow when the Ball grid Array contact (36) is attached to a contact (31) on a printed circuit board (30) that has a via (32) extending at least partially though the printed circuit board (30). A solder form (35) is placed over each via (32) in each contact (31) of the contact array. The electronic component (40) that has BGA contacts (36) is placed over the contact array (31) such that each ball (36) of the ball grid array of the electronic component resides on a solder form (35). The component (40) and circuit board (30) is subjected to a solder reflow process to seal the component (40) to the circuit board (30). The solder form (35) at least partially fills the via (32) preventing the BGA contact (36) from collapsing into the via (32).

Abstract: A processor (100) is provided that is a programmable digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Instructions may be executed during delay slots after program branching while an execution pipeline is being restarted. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. A software breakpoint instruction is provided for debugging purposes. In order to correctly emulate the operation of the instruction pipeline when a software breakpoint instruction is executed during a delay slot, the width (1110-1115) of the software breakpoint is the same as the replaced instruction. A limited number of breakpoint instruction length formats (1100, 1102) are combined with non-operational instructions (NOP, NOP—16) to form a large number of combination instructions that match any instruction length format.

Abstract: Startup operation of a DC/DC switching regulator is controlled by providing a first signal (MAXDC) whose waveform has a duty cycle that varies over time, providing a second signal (620, 622) indicative of a load condition of the regulator, and combining the first and second signals to produce a third signal (312, 311). The third signal is used to control a power switch (231, 324) of the regulator.

Abstract: An organically modified dielectric network structure (208) and solid halide-containing material (206) are co-deposited using a chemical vapor deposition process. The solid halide-containing material (206) is then sublimated leaving a porous dielectric (212). An encapsulating layer (210) is formed over the porous dielectric (212) to seal any remaining halide-containing material Within the porous dielectric (212).

Abstract: A power-up control circuit architecture that utilizes zero current under normal operation. The power-up control circuit will sense a common supply voltage, Vcc, and turn an output on and off at a desired threshold voltage, providing a substantially faster on/off switch than that achievable solely by sensing the common supply voltage.

Abstract: An IEEE 1394 serial bus (58) is interfaced utilizing a physical layer (54) to extract the data and a link/transaction layer controller (200) to interface the data from the physical layer (54) to a host system. The host system consists of a peripheral device (210) which is interfaced with various host buses (202). The link/transaction layer controller (200) is operable to emulate the microcontroller function such that addresses can be transmitted to the peripheral device (210) along with data, such that a remote node can access the peripheral device (210) by transmitting address and data information thereto. Alternatively, address and data information can be transmitted from the peripheral device (210) to the controller (200) which will process the received address and data and transmit it to a remote node.

Abstract: A method for fabricating a phase shift photomask (10) includes providing a photomask (12) having a substantially opaque layer (16) on a surface (14) of a substantially transparent substrate (18). The opaque layer (14) includes a removed portion to define a light transmitting pattern (20) of the photomask (12). The method also includes depositing an implant (22) in a portion of the substrate (18). The implanted portion (24) of the substrate (18) includes an etch rate different than an etch rate of an unimplanted portion (32) of the substrate (18). The method includes initiating an etch of the substrate (18) corresponding to the light transmitting pattern (20) and monitoring a rate of the etch. The method further includes terminating the etch in response to detecting a change in the rate of the etch.

Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

Abstract: A light-sensing diode fabricated in a semiconductor substrate having a surface protected by an insulator, comprising a first region of one conductivity type in this substrate, a second region of the opposite conductivity type forming a junction with the first region in the substrate; this junction having a convoluted shape, providing two portions generally parallel to the surface, and a constricted intersection with the surface; and a gate for applying electrical bias across the junction, this gate positioned on the insulator such that it covers all portions of the junction intersection with the surface, thereby creating a gate-controlled photodiode.

Abstract: An FET and DRAM using a plurality of such FETs wherein each transistor has a body region of a first conductivity type including a relatively high VT region and relatively low VT region, the high VT region disposed contiguous with the low VT region. A pair of source/drain regions of opposite conductivity type are disposed on a pair of opposing sides of each of the low VT region. The transistor includes a gate oxide over the body region and a gate electrode over the gate oxide and spaced from the body region. The body region is p-doped or n-doped with the high VT region more heavily doped than the remainder of the body. In a further embodiment, the FET includes a body region of a first conductivity type which includes a relatively low VT region and a first pair of relatively high VT regions on a first pair of opposing sides of the body. A pair of source/drain regions of opposite conductivity type are disposed on a second pair of opposing sides of each of the low VT region.

Abstract: A digital-to-analog (D/A) converter with a required accuracy can be implemented in a smaller chip area and at a lower cost. The D/A converter comprises a decoder which receives a digital input signal comprised of a first number of bits, and divides the first number of bits into a second number of bit groups. Bit group converters equal in number to the second number, are provided for the second number of bit groups, and each selects and uses a form of weight for each of the bit groups associated therewith to convert the bit group into an analog form in response to the second number of bit groups, thereby generating the second number of bit group analog outputs. An adder adds the second number of the bit group analog outputs to form an analog signal output representative of the digital signal input.

Abstract: An improved pre-driver circuit 33, which uses only three additional components to bypass the back-gate current blocking diodes for increased circuit speed during normal operation, while reducing the Ioff current and satisfying over-voltage tolerant specification. This unique circuit uses the pre-driver's tri-state input signal to control the pull-up path of the pre-driver circuit's upper output (UOP) transistor 3010.

Abstract: A different amplifier with rail-to-rail input including a single differential transistor pair utilizes a feedback circuit to control the threshold voltage of the differential transistor pair in accordance with the common mode voltage. The threshold voltage is controlled by adjusting the body bias coefficient with respect to the base to source voltage of the transistors.

Abstract: An optocoupler structure comprising a semiconductor chip having an integrated circuit and an optically transparent, electrically insulating layer having first and second surfaces; an organic diode integral with said first surface, said diode operable to emit electromagnetic radiation; and said circuit including a radiation-sensitive semiconductor device integral with said second surface, electrically isolated from said diode, and positioned in the path of said radiation.

Abstract: A Java television receiver (10) includes a Java television platform (12) that has a bidirectional Internet connection (14) capable of sending Internet data to the Java television platform (12) and transmitting data from the Java television platform (12) to an Internet provider. Additionally, a tuner/decoder (24) connected to the Java television platform (12) is provided which can receive, tune and decode television signals. An audio/video overlay (32) connected to the Java television platform is provided to combine displays from the Java television platform (12) and television signals from the tuner/decoder (24). Finally, a video output (36) and an audio output (38) sends the combined Internet data and television signals to a television (40).

Abstract: A system and method is provided for monitoring a voltage level of a charge pump device. The system and method employ a first charging device that is coupled to an output of a charge pump through a switching system. The first charging device is then decoupled from the output of the charge pump device and coupled to a second charging device. The charge on the first charging device is then redistributed between the first charging device and the second charging device. The output of the second charging device is a reduced voltage (e.g., below 5 volts) based on the ratio of the charge distribution between the first and second charging devices. The output of the second charging device can then be compared to a reference voltage to determine if the voltage of the charge pump device is at an adequate voltage level.

Abstract: An apparatus detects the presence or absence of a semiconductor device. The apparatus includes a wire bonding machine to form a connection with the semiconductor device, and a camera to form an image of a position of the semiconductor device. A processor controls the wire bonding machine and transforms the image to pixel data. Additionally, the processor converts the pixel data to discrimination data to indicate whether the semiconductor device is present. The processor controls the wire bonding machine in accordance with the presence or the absence of the semiconductor device.

Abstract: An asymmetry correction circuit for correcting an asymmetry signal includes a first transconductance circuit for transforming the asymmetry signal to a bias current in a first current path, a second transconductance circuit to form the bias current in a second current path, and a feed-forward circuit for transforming the asymmetry signal to a positive difference current and a negative difference current.

Abstract: A method and apparatus for performing gain calibration of an analog to digital converter is provided. During a calibration mode, an input sampling circuit comprised of multiple branches can be configured to provide a calibration mode gain of one. The analog-to-digital converter selects one of the parallel capacitor input sampling branches and repetitively samples the whole charge associated with the calibration voltage signal. This sampling step is repeated for each input sampling branch that is used during normal operation mode. The results of the sampling of the branches may be suitably averaged to create a gain calibration coefficient that is representative of and accounts for sampling variations between the input branches.

Abstract: A linear regulator circuit to regulate an output voltage includes a first current path to conduct a first current, a feedback path to provide feedback to maintain the output voltage at a constant voltage, and a transistor positioned in the first current path to provide the output voltage.