Abstract: A Page Address Look-up Range RAM is disclosed which allows for individual comparisons to be made on a number of consecutive addresses. The upper bits of the bus address 410 (often representing a “page”) are compared against one or more reference registers 430-437 to yield one or more “match_high”s. The lower bits of the same bus address 420 are used to look-up the value of “match_low” in a Page Look-Up RAM 440, the bit of interest corresponding to the particular “match-high” reference register i.e. 430. If both the “match_high” and “match_low” events are true, or=1, then the bus address has matched and should cause the event, otherwise not. The most cost effective implementations will have a Look-up RAM 440 with a width of a multiple of 8. This will allow comparison of the bus address against a multiple of individual pages.

Abstract: A low-cost ceramic package, in land-grid array or ball-grid array configuration, for micromechanical components is fabricated by coating the whole integrated circuits wafer with a protective material, selectively etching the coating for solder ball attachment, singulating the chips, flip-chip assembling a chip onto the opening of a ceramic substrate, underfilling the gaps between the solder joints with a polymeric encapsulant, removing the protective material form the components, and attaching a lid to the substrate for sealing the package. It is an aspect of the present invention to be applicable to a variety of different semiconductor micromechanical devices, for instance actuators, motors, sensors, spatial light modulators, and deformable mirror devices. In all applications, the invention achieves technical advantages as well as significant cost reduction and yield increase.

Abstract: A solid-state imaging device having contacts for a charge sweeping component or the like, with which increases in dark current can be suppressed while increases in contact resistance and the production of alloy spikes can be prevented, and a method for manufacturing this device. A solid-state imaging device has a charge accumulator for producing and accumulating signal charges when light is received, and a charge transfer component for transferring these signal charges, including a conductive layer 18 formed on a substrate 10, such as a silicon layer or metal wiring; an insulating film 21 formed over the conductive layer 18; an opening CH formed over the insulating film 21 and leading to the conductive layer 18; and a wiring layer 34 composed of aluminum containing copper in an amount between 0.4 and 5 wt %, formed at least inside the opening CH contiguously with the surface of the conductive layer 18.

Abstract: Methods and apparatus are disclosed for reducing output ripple voltages in bandgap voltage reference circuits. Ripple rejection circuitry is connected to a supply voltage and a first control signal, such as from an amplifier. The ripple rejection circuitry provides a second control signal representative of a difference between the supply voltage and the first control signal. The second control signal is then used to generate a reference voltage output. The incorporation of the supply voltage component in the second control signal operates to reduce or suppress the effects of power supply ripple on the bandgap voltage output.

Abstract: A processor (100) is provided that is a programmable digital signal processor (DSP) with variable instruction length. A trace FIFO (800) is provided for tracing a sequence of instruction addresses to assist with software or hardware debugging. In order to conserve space, only the addresses of an instruction just before (M+K, P+Q) and just after (P, R) a discontinuity are stored in the trace FIFO. A sequence of instruction lengths (SEC13LPC) is also stored in the trace FIFO so that the sequence of instruction addresses can be reconstructed by interpolating between two discontinuity points (P to P+Q).

Abstract: A method of photolithographically patterning an organic semiconductor device, comprising the steps of protecting the organic layer of the device by depositing a metal layer thereon, depositing and patterning a photoresist layer on said metal layer, and selectively etching the exposed areas to pattern said metal layer and said organic layer. Specifically, the disclosed method provides the photolithographic fabrication of organic light emitting diodes (OLEDs) and organic lasers diodes (OLDs).

Abstract: A temperature-compensated monolithic logarithmic amplifier includes a logarithmic amplifier cell (26) configured to produce a logarithmic voltage signal (V3) representative of a difference between a first voltage (V1) developed across a first PN junction device (D1) in response to an input signal (Iin) and a second voltage (V2) developed across a second PN junction device (D2) in response to a reference signal (Iref) and an output circuit (36) including an output amplifier (19), a temperature-dependent first resistive element (R1) having a positive temperature coefficient, and a second resistive element (R2). The output circuit (36) produces a temperature-compensated output signal (Vout) in response to the logarithmic voltage signal (V3). The first resistive element (R1) is composed of conductive aluminum or aluminum alloy interconnection metallization that also is utilized as interconnection metallization throughout the monolithic logarithmic amplifier.

Abstract: The present invention provides a dual stage amplifier with a clamping circuit and a methodology, along with a clamping circuit for use with a dual stage amplifier, which eliminate or reduce the overcharging of a compensation capacitor in such a dual stage amplifier. The amplifier includes a first amplifier stage with a first input and a first output, a second amplifier stage having a second input operatively connected to the first output, and a second output. The amplifier further includes a compensation capacitor in electrical communication with the second input and the second output, and a clamping circuit in electrical communication with the second stage, which is adapted to prevent overcharging of the compensation capacitor.

Abstract: An embodiment of the present invention is a method of forming an ultra-thin dielectric layer, the method comprising the steps of: providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer to a nitrogen-containing plasma to create a uniform nitrogen distribution throughout the oxygen-containing layer; and re-oxidizing and annealing the layer to stabilize the nitrogen distribution, heal plasma-induced damage, and reduce interfacial defect density. This annealing step is selected from a group of four re-oxidizing techniques: Consecutive annealing in a mixture of H2 and N2 (preferably less than 20% H2), and then a mixture of O2 and N2 (preferably less than 20% O2); annealing by a spike-like temperature rise (preferably less than 1 s at 1000 to 1150° C.

Abstract: A method of fabricating an integrated circuit having active components, conductors and isolation regions on a substrate is disclosed, including forming a portion of an isolation region to expose a first area of the substrate, depositing a mask layer over the integrated circuit including the first area, forming the mask layer to expose a second area of the substrate within the first area, converting a portion of the substrate to a selectively etchable material in an area subjacent to the second area and extending only partially to the bottom surface of the substrate, selectively etching this etchable material to form a void, removing the mask layer to expose the isolation region, depositing a conductive layer over all exposed surfaces of the substrate comprising the void and the isolation region, depositing a dielectric layer over the conductive layer extending at least to the height of the isolation region, polishing the surface of the dielectric layer until the surface is planar and the top surface of the is

Abstract: A battery protection device (10) has a hollow casing body (11) formed by ultrasonic welding of a first casing member (12) and a second casing member (13) with respect to casing body (11), a first external terminal extends from a first end surface (11b) and a second external terminal extends from a second end surface (11c). The battery protection device (10) further has a first contact (18) connected to the first external terminal, a second contact (16) connected to the second external terminal, and a bimetallic member (17) which enables the connection between and first and second contacts to be opened and closed. In a second embodiment one of the casing member (72) is formed of a sheet of electrically insulative material which is received over and closes the opening in the other casing member (71).

Abstract: A circuit for multiplexing a selected one of a plurality of input signals to an output conductor includes a plurality of diamond follower input buffers each having an input terminal coupled to receive an input signal, respectively. A diamond follower output buffer has an output coupled to the output conductor. A feedback resistor is coupled between the output conductor and the outputs of the input buffers. A first current mirror has a control input coupled to a first current bias terminal of each input buffer, and a second current error has a control input coupled to a second current bias terminal of each input buffer. The first and second current mirrors have outputs connected to drive the input of the output buffer and bias current terminals of the output buffer to provide a high slew rate.

Abstract: An apparatus and method for automatically detecting defects on silicon dies on silicon wafers comprising a silicon wafer acquisition system (30) and a computer (32) connected to said silicon wafer image acquisition system (10), wherein said computer (32) automatically aligns a silicon wafer (16), calibrates the image acquisition system (30), analyzes die images by determining a statistical die model from a plurality of dies, and compares the statistical die model to silicon die images to determine if the silicon dies have surface defects, is disclosed.

Abstract: A semiconductor device comprising a lead frame that includes a large area mount pad having small elevated pads to which a semiconductor chip is attached. The small mount pads coupled with usage of a minimal amount of chip attach adhesive provide improved reliability against vapor phase package cracking, and further allow a given lead frame to be used by a family of chip sizes and shapes. The large pad provides good thermal dissipation, as well as stress relief during fabrication of the lead frame.

Abstract: A microelectromechanical (MEM) device with an expanded PTFE material over the gap between movable structures to provide electrical connection across the gap and prevent particles from contaminating the gap. A microelectromechanical (MEM) device is also immobilized by placing an expanded PTFE material over the gap between movable structures. The expanded PTFE material can be made stiff during manufacture and then flexible after the manufacturing process is complete. An embodiment of the invention is a MEM device configured as a micro-actuator for a dual-actuator hard disk drive.

Abstract: A method and apparatus for characterizing a magnetic disk (40) of the type that contains data to be read by a magneto-resistive type head (18) in proximity thereto is disclosed. The method includes writing a continuous signal onto the disk, and reading back the signal written onto the disk (40) using the magneto-resistive type head (18). The read back signal is compared to a threshold value (58), and areas of said disk at which energy contained in said read back signal occurs above said threshold value (54) are mapped. The energy content is measured by accumulating oversampled signal values from the read back signal during a time at which said read back signal exceeds the threshold value (58).

Abstract: A low gain feedback compensation circuit is provided on an integrated circuit. The feedback compensation circuit is coupled to a step down power supply on the integrated circuit. The step down power supply is operable to receive an input voltage and to generate an output voltage based on the input voltage. The feedback compensation circuit includes a line regulation circuit. The line regulation circuit is operable to receive the input voltage and a reference voltage. The line regulation circuit is also operable to generate an offset voltage based on the input voltage and the reference voltage.

Abstract: A photodiode sensor (25) has a photodiode (30) with an associated capacitance (34), which may be a parasitic capacitance of the photodiode (30). A switch (36) is provided for charging the capacitance (34) to a predetermined reset voltage (Vreset) such that when light impinges upon the photodiode (30), the voltage on the capacitance (34) discharges in a time proportional to an intensity of the light. A circuit (42) is also provided for measuring the time for the capacitance (34) to discharge to a predetermined threshold value (33), which may be a function of time. The voltage on the output (38) of the comparator (28) may be sampled, with the sampling period also being variable as a function of time. The image may be reconstructed from time data indicating the relative times that discharge voltage of the pixels in an array cross the reference voltage (33).

Abstract: Disclosed is a method for generating patterns to be used in a spatial light modulator having a plurality of pixels. The method includes generating an optical pattern to be placed upon the pixels of the spatial light modulator, applying the optical pattern to the pixels of the spatial light modulator, measuring the optical performance of the plurality of pixels having the optical pattern applied to it, comparing the measured optical performance to a target optical performance, and adjusting the optical pattern applied to the plurality of pixels to form another optical pattern that more closely achieves the target optical performance.

Abstract: A lateral NPN transistor (LPNP) (102) having the lightly doped drain extension implant blocked from the emitter region (118) but not the collector region (120). Accordingly, the emitter region (118) has a more abrupt junction for high emitter injection efficiency while the collector region (120) has a lightly doped region for reduced base depletion.