Abstract: The circuit configuration for the generation of clock signals for a semiconductor memory (14) that are edge-synchronous with the output signals of a clock generator (16) comprises an input stage (20) to which the output signals of the clock generator (16) are applied. It furthermore contains a phase detector (30) which receives the signals output by the input stage (20) and whose output signals control a voltage-controlled oscillator (34) which supplies the clock signals for the semiconductor memory (14). It also contains a conversion stage (42) which applies signals related to the output signals of the oscillator (34) to the phase detector (30), which controls the oscillator in such a way that the phase difference between the signals reaching it from the input stage (20) and the signals also reaching it from the conversion stage (42) becomes zero. The input stage (20) comprises an amplifier (44) containing a circuit component (62) capable of influencing the signal transit time.

Abstract: The present invention relates to a method of providing error margin information for threshold errors associated with a digital peak detector. The method comprises comparing a plurality of peak sample values associated with the digital peak detector to a threshold margin test level and incrementing a counter each time the threshold margin test level exceeds one of the plurality of peak sample values. The value associated with the counter relates to an amount of threshold margin associated with the digital peak detector. The present invention also relates to a method of providing error margin information for peak shift errors associated with a digital peak detector. The method comprises identifying relevant peak sample data points associated with each of a plurality of detected peaks and determining a peak shift amplitude associated with each of the detected peaks using the identified relevant peak sample data points.

Abstract: A processor (100) is provided that is a programmable digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. Two sets of interrupt vectors are maintained. Interrupts vectors pertaining to interrupts originated by one set of interrupt sources (820, 821, 822) are stored in a DSP interrupt vector table (850) located in a memory circuit 801 that is private to the DSP. Interrupt vectors pertaining to interrupts originated by a host processor (810) are stored in a Host interrupt vector table (851) located in a dual ported communication memory circuit (802). The DSP executes interrupt service routines to service all of the interrupts, but the host can change the interrupt vectors for host initiated interrupts.

Abstract: A display system (800) combining light from two sources into a single light beam that is modulated by a light valve to form an image. Light from a first light source (802) is anamorphically focused along a first light path by a first lens group (804) and a second lens group (806). The first and second lens groups are typically cylindrical lenses having perpendicular axes. The two lens groups focus the light from the first light source onto an integrating rod (808). In a similar manner, light from a second light source (810) is anamorphically focused along a second light path by a first lens group (812) and a second lens group (814) onto the same integrating rod (808). Light from the integrating rod (808) illuminates a light valve (816). Light valve (816) typically is a micromirror device or a liquid crystal panel. The light valve modulates the light from the integrating rod (808) to form a modulated light beam that is focused by projection optics (822) onto an image plane (824).

Abstract: An apparatus and method for utilizing a correction loop amplifier in conjunction with a main amplifier to produce signal amplification with low total harmonic distortion. The correction amplifier preferably has one input directly coupled to a first input of the main amplifier, and an output coupled to a second input of the main amplifier via a resistor. The second input of the correction amplifier is preferably coupled to a signal input via a voltage divider or RC network. A preferred embodiment configuration provides a power amplifier with improved THD over prior art circuits. The circuit is very flexible, and may incorporate low, high or band pass filter functions if desired. In addition, the power amplifier may be implemented in any combination of single or differential inputs and outputs.

Abstract: A pipeline analog to digital converter that includes a main pipeline including a plurality of analog to digital converter stages and a shadow pipeline for compensating the output of the main pipeline. Each of the analog to digital converter stages in the main pipeline provides a digital output and an analog residue signal. The shadow pipeline includes one or more stages that receive at least one gain error signal from one of the analog to digital converter stages in the main pipeline. The shadow pipeline is configured and arranged to processes the gain error signal to form a compensation signal. The compensation signal is combined with the analog residue signal to provide a compensated residue signal in which the finite error gain has been substantially removed.

Abstract: A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the decreases a reduction in a bottom electrode material during formation of the ferroelectric dielectric portion of the capacitor. In the above manner, a fatigue resistance of the ferroelectric capacitor is increased substantially.

Abstract: A class ‘AB’ amplifier output stage has an active current bias source that provides base drive current to the output transistors that is proportional to the signal input voltage level. The output transistor currents are modulated with the input signal such that the quiescent supply current is reduced to a very small level.

Abstract: A pipelined data converter current biasing system employs a frequency-to-voltage converter (FVC) operational to convert a plurality of desired sampling frequencies to a plurality of output voltages and a voltage-to-current (V to I) converter operational to convert the plurality of output voltages to a plurality of bias currents. The plurality of bias currents function to bias the data converter operational amplifiers such that the data converter power consumption is dependent on the plurality of sampling frequencies in a way that optimizes power consumed by the data converter with respect to the sampling frequency.

Abstract: The buffer/driver for low dropout regulators (LDO) uses a feedback amplifier with low output impedance to drive the gate of the pass device MP6 of the regulator. This effectively pushes the gate pole out to a higher frequency. The feedback amplifier is designed for very high slew rate and high bandwidth while running at very low quiescent current. The circuit enhances the LDO performance, stability, and slew rate.

Abstract: A post write buffer for a dual clock system which improves the utilization of host data bus (10) bandwidth is provided which consists of an address buffer (60), a data buffer (62), a first clock timing signal (22), a second clock timing signal (48), an address decoder (24), a first write enable circuit (72), and a second write enable circuit (74). The address-buffer (60) and data buffer (62). hold the data and the destination address for that data until the clock signals are synchronized and the data is ready for transfer. The address decoder (24) determines which destination register byte will receive the data in the host data bus (10). The write enable circuits (72, 74) synchronize the clock signals (22, 48) and determine when the destination register is ready to receive the data from the data buffer (62).

Abstract: A phase comparison circuit capable of realizing high-speed response by the PLL circuit in order to realize high-speed reproduction of the signals. An input signal is delayed by a delay buffer in order to produce a delayed signal. Changes in the level of the input signal are detected by a leading edge detection circuit and a falling edge detection circuit, a first and a second edge detection signals are output a control circuit changes the level of an output signal according to these detection signals, a phase comparison circuit compares the phases of the output from the control circuit and the clock signal, and a first and a second control signals are output according to the comparison result.

Abstract: A system and method are disclosed including a vapor dryer chamber (12) with a lid (14). A heater (16) is disposed within the vapor dryer chamber to vaporize liquid drying medium (24), preferably isopropyl alcohol, in the bottom of the vapor dryer chamber (12). Cooling coils (18) disposed within an upper portion of the vapor drying chamber (12) condense the drying medium vapor. A vapor monitor assembly (30) is disposed within the vapor dryer chamber (12) to monitor the vapor concentration within vapor dryer chamber (12). A controller (40) is associated with the vapor monitor assembly (30) and evaluates vapor concentration measurements from the vapor monitor (38).

Abstract: A method for integrating a thin film resistor (60) into an interconnect process flow. Metal interconnect lines (40) are formed over a semiconductor body (10). An interlevel dielectric (50) is then formed over the metal interconnect lines (40). Conductively filled vias (62) are then formed through the interlevel dielectric (50) to the metal interconnect lines (40). A thin film resistor (60) is then formed connecting between at least two of the conductively filled vias (62) using a single mask step. Connection to the resistor (60) is from below using a via process sequence already required for connecting between interconnect layers (40, 64). Thus, only one additional mask step is required to incorporate the resistor (60).

Abstract: A processor (100) is provided that is a programmable digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. An instruction (1003) is decoded and accesses a data item in accordance with an address field (1003a). Another instruction (1002) is decoded and accesses a data item in accordance with an address field (1002a); but in a different manner due to an instruction qualifier (1002b). The instruction qualifier is executed in an implicitly parallel manner with the qualified instruction (1002).

Abstract: An antenna network system comprises a server including a transmitter and an antenna, and a client including a receiver and a steerable antenna. There is also included a control path which is independently operable of the antennas for communicating control data between the server and client. The server is responsive to signal quality data communicated via the control path for steering at least one of the server antenna and client antenna in a direction for optimising the signal quality of communications transmitted between them.

Abstract: In deep submicron technologies, coupling capacitance significantly dominates the total parasitic capacitance. This causes crosstalk noise to be induced on quiescent signals which could lead to catastrophic failures. A methodology is provided that is a practical approach to full-chip crosstalk noise verification. A grouping based method is described for identification of potential victims and associated aggressors, using either timing information or functional information. Potential victim signal lines are selected and pruned based on total coupling capacitance to various signal groups.

Abstract: An apparatus and method for evaluating semiconductor structures and devices are provided. A method for evaluating at least one selected electrical property of a semiconductor device (201) in relation to a selected geometric dimension of the semiconductor device (201). The method further includes forming a plurality of semiconductor devices (201) on a substrate (202), the devices (201) having at least one geometric dimension, measuring the at least one electrical property of at least one of the semiconductor devices (201) using a scanning probe microscopy based technique, and determining a relationship between the measured electrical property and the selected geometric dimension of the semiconductor device (201). The method further includes evaluating at least one semiconductor fabrication process based upon the determined relationship.

Abstract: A supply reference voltage circuit is coupled to an output node, a supply voltage node and a supply reference voltage node and is operable to connect the output node to the supply reference voltage node and prevent current flow through an output device coupled to the output node in response to sensing a low voltage level at the supply voltage node and a non-zero voltage at the output node. The circuit is further operable to connect the supply reference voltage node to the supply voltage node in response to the voltage at the output node being a threshold voltage above the voltage at the supply voltage node. The circuit is further operable to bypass a blocking diode in response to sensing a high voltage level at the supply voltage node.

Abstract: A serial and parallel data communication system utilizing a data forwarding element and a data forwarding multiplexer; providing a method of data conversion having an overlap in the operation of parallel and serial I/O modes. The present invention thus enables continuous and simultaneous serial to parallel and parallel to serial conversion.