Abstract: A serial and parallel data communication system utilizing a data forwarding element and a data forwarding multiplexer; providing a method of data conversion having an overlap in the operation of parallel and serial I/O modes. The present invention thus enables continuous and simultaneous serial to parallel and parallel to serial conversion.

Abstract: A bias rail buffer circuit and method in accordance with the present invention overcomes many shortcomings of the prior art. A bias rail buffer circuit for providing a reference signal is suitably configured to absorb external disturbances appearing on an output reference signal. A method for absorbing the external disturbances appearing at the output reference signal suitably includes the use of complementary transistors to source current and sink current to said output reference signal, depending on whether the external disturbances are providing a decrease or an increase to the output reference signal. The bias rail buffer circuit suitably includes an input transistor, a first pair of complementary transistors and a second pair of complementary transistors, such that the second pair of complementary transistors operate to source current and sink current to absorb external disturbances imparted on said output reference signal.

Abstract: A circuit is provided that can provide, in a single package, a means to monitor a sensing element which uses a variable resistor. The circuit (also known as a signal conditioning circuit) may contain resistor input terminals to which a reference set resistor and a resistive sensor can be attached. A reference voltage signal can be applied to both terminals. There are also means for sensing the resulting current flowing through both the set resistor and the resistive sensor. The difference of the currents flowing through each element can then be monitored as being indicative of the difference in resistance between the set resistor and the resistive sensor. The current difference signal can be used to generate a voltage difference signal indicative of the difference in resistance between the set resistor and the resistive sensor. The signal conditioning circuit may be used to adjust the temperature of various devices.

Abstract: A power amplifier controller (45) for a wireless communications device (10), such as a wireless telephone, is disclosed. The power amplifier controller (45) has includes controllable bias current sources (56, 58) coupled to Schottky diodes (60), which are coupled to power amplifiers (50) to sense their power output. The controllable bias current sources (56, 58) selectably apply one of multiple available bias currents (I1, I2) to their corresponding Schottky diodes (60F, 60R). Timing and control circuitry (62) in the power amplifier controller (45) receives a desired power level signal (DESPWR), and control switches (SW1, SW2) in the controllable bias current sources (56, 58) to apply a bias current (I1, I2) responsive to the level of power indicated by the desired power level signal (DESPWR). The power detected by Schottky diodes (60F, 60R) is applied to a summing adder (65), from which a control signal (VAPC) is derived and used to control the output of the power amplifiers (50).

Abstract: Linearity of an n-bit integrated resistor string is improved by arraying the 2n resistors in 2k columns of 2m series coupled resistors each. The 2k columns of resistors are grouped in 2g groups of serially coupled columns of resistors with the total resistance of each group of columns of resistors substantially the same as the total resistance of each of the other groups of columns of resistors.

Abstract: A highly miniaturized nanomechanical transistor switch is fabricated using a mechanical cantilever which creates a conductive path between two electrodes in its deflected state. In one embodiment, the cantilever is deflected by an electrostatic attraction arising from a voltage potential between the cantilever and a control electrode. In another embodiment, the cantilever is formed of a material with high magnetic permeability, and is deflected in response to complementary magnetic fields induced in the cantilever and in an adjacent electrode. The nanomechanical switch can be fabricated using well known semiconductor fabrication techniques, although semiconductor materials are not necessary for fabrication. The switch can rely upon physical contact between the cantilever and the adjacent electrode for current flow, or can rely upon sufficient proximity between the cantilever and the adjacent electrode to allow for tunneling current flow.

Abstract: In one form of the invention, a process of sending real-time information from a sender computer to a receiver computer coupled to the sender computer by a packet network wherein packets sometimes become lost, includes steps of directing packets containing the real-time information from the sender computer by at least one path in the packet network to the receiver computer, and directing packets containing information dependent on the real-time information from the sender computer by at least one path deversity path in the packet network to the same receiver computer.

Abstract: A sorting device for a variable-length code containing the following parts: a coding part 43 that converts the length value to a first bit column according to its value, a first shifter 44 that converts the first bit column input from said coding part 43 to a second bit column according to the shift parameters, a second shifter 42 that converts the code value to a third bit column according to the shift parameter, and a register 45 that has the second bit column input from said first shifter 44 and the third bit column input from said second shifter 42, and which outputs only the content of the bit at the position of the third bit column corresponding to the position of the bit indicating the prescribed value “1” of the second bit column.

Abstract: A semiconductor device and process for making the same are disclosed which use reticulated conductors and a width-selective planarizing interlevel dielectric (ILD) deposition process to improve planarity of an interconnect layer. Reticulated conductor 52 is used in place of a solid conductor where the required solid conductor width would be greater than a process and design dependent critical width (conductors smaller than the critical width may be planarized by an appropriate ILD deposition). The reticulated conductor is preferably formed of integrally-formed conductive segments with widths less than the critical width, such that an ILD 32 formed by a process such as a high density plasma oxide deposition (formed by decomposition of silane in an oxygen-argon atmosphere with a back-sputtering bias) or spin-coating planarizes the larger, reticulated conductor as it would a solid conductor of less than critical width. Using such a technique, subsequent ILD planarization steps by e.g.

Abstract: The transfer controller with hub and ports (TCHP) performs the task of communication throughout an entire system in a centralized function. A single hub (435) tied to multiple ports (440, 447, 450, 452) by a central pipeline is the medium for all data communications among DSP clusters (455), external devices, and external memory. A transfer request queue manager (420) receives, prioritizes and queues data transfer requests. Each data port includes an identically configured interior interface (901) connected to the hub (435) and an exterior interface (902) configured for a target external memory/device connected to the port. The interior interfaces of all ports are clocked at a common internal frequency, while the exterior interfaces are clocked at the frequency of the external memory/device connected to the port.

Abstract: A write driver controls current path for current of an H-bridge circuit. The H-bridge circuit is controlled by a differential pair switch for adjusting a voltage between the differential pair switch between a first voltage when the H-bridge circuit is switched and a second voltage after the H-bridge circuit is switched.

Abstract: A start-up switch 50 for an electric motor 1 comprises a resistive element (54) which is so constituted as to be connectable to an electric current path (15) and which has such a characteristic that its resistance value increases by the heat generated by electric current that flows through the electric current path (15) and a thermostatic switch (60) which is connected in series with the resistive element (54). The thermostatic switch (60) has an actuation member (60) which is responsive to temperature so that upon reaching a preselected temperature, said member moves from a closed current path position to an open current path position. The thermostatic switch (60) is positioned to be in direct heat transfer relationship with the resistive element (54) so that the member will (66) rise in temperature as the resistive element (54) rises in temperature.

Abstract: A post-in-crown capacitor is disclosed. The post-in-crown capacitor (60) includes a crown (44) coupled to a conductive via (20). A post (48) is disposed within the crown (44) and a capacitor insulation layer (50) is formed outwardly from the crown (44) and the post (48). A capacitor plate layer (52) is then formed outwardly from the capacitor insulation layer (50).

Abstract: A digital driver circuit with one or more CMOS inverters intended as input stages, whereby for the MOS FETs of the inverters the channel width/length (W/L) ratio increases from stage to stage. The digital driver circuit includes an intermediate stage with two further CMOS inverters, connected between a supply voltage Vcc and ground. The driver circuit also includes an output stage having two MOS FETs with the drain terminals of both the MOS FETs of the output stage connected both to each other and to the output of the circuit, the W/L ratio of both MOS FETs exceeding that of the MOS FETs of the intermediate stage. The switch-over of the two MOS FETs of the output stage, occurring with changes of the digital input signal at the input of the circuit, is offset in time with respect to each other, thereby reducing current peaks.

Abstract: A synchronous switching DC-DC regulator uses the output switching node as the control reference for the main FET gate drive voltage limiting and the appropriate on-time gate drive FET as the controlled switch. The control reference provided by the output switching node times the main FET gate drive voltage setting process and supplies most of the energy necessary to turn on the main FETs. The energy is provided in part from an external inductor coupled to the output switching node.

Abstract: A combination NAND and flip-flop circuit includes a pre-NAND scan circuit operable to receive a plurality of input signals and produce first and second output signals for receipt by a NAND gate. The plurality of signals comprises signals indicative of a first data signal, a second data signal, a scan-in signal, and a scan-enable signal. These circuits include a NAND gate having first and second inputs operable to receive the first and second output signals of the pre-NAND scan circuit. They also include a first transmission gate and a first inverter. The transmission gate receives the output of the NAND gate and the inverter receives the output of the transmission gate. The pre-NAND scan circuit is operable to produce the first and second output signals based on the plurality of input signals such that the first and second output signals are defined as described below.

Abstract: In deep submicron technologies, coupling capacitance significantly dominates the total parasitic capacitance. This causes crosstalk noise to be induced on quiescent signals which could lead to catastrophic failures. A methodology is provided that is a practical approach to full-chip crosstalk noise verification. A multi-dimensional noise lookup table is formed for a cell used within the IC, wherein the multi-dimensional noise table relates a set of input noise pulse characteristics and a set of output loading characteristics to an output noise pulse characteristic of the cell. A noise pulse on an input to an instantiation of a cell is determined and then characterized. An output loading characteristic of the cell is also made. A prediction of whether the instantiation of cell will propagate the noise pulse is made by selecting an output noise pulse characteristic from the multi-dimensional noise table corresponding to the noise pulse characteristic and to the output loading characteristic.

Abstract: For quantitatively identifying sensitivities against electrostatic discharge (ESD) and latch-up in an integrated circuit (IC) design (before the actual IC is fabricated), the disclosed computer system and method combine information from the design netlist, the elements model, a safe operating file, and a list of stress simulations, and apply a simulated, quantified ESD event to the design. The observed sensitivities of the design elements to ESD and latch-up are then quantitatively analyzed, critical stress values are judged, and element failures recorded. Finally, element and location lists of sensitivities and failures are output in a specific format.

Abstract: This invention is a data synchronous apparatus for synchronization between a first clock domain to a second clock domain asynchronous with the first clock domain. This invention provides for pipelining of data between the two clock domains. Plural synchronizer stages each include a data register (601, 602, 603, 604, 605) and a synchronizer circuit (611, 612, 613, 614, 615). The synchronizer circuit synchronizes a first domain write request signal to the second clock signal. A write pointer (625) enables one synchronizer stage to write first domain data upon receipt of said first domain write request signal (321). The write pointer thereafter increments to indicate a next synchronizer stage in a circular sequence. A read pointer (635) enables an indicated read stage to recall data from the corresponding data register upon output synchronization with the second clock signal. The read pointer thereafter increments to indicate the next synchronizer stage in the circular sequence.

Abstract: An embodiment of the instant invention is a method of fabricating a ferroelectric memory device (125 of FIG. 1) comprised of a top electrode (128 and 130 of FIG. 1) over a bottom electrode (124 of FIG. 1) with a ferroelectric material (126 of FIG.