Abstract: A new family of current mode logic (CML) gates (14) which, in one embodiment includes OR/NOR and AND/NAND gates, as well as more complex logic functions. The circuit uses a complementary signal to drive the gate of a feedback transistor (19) which has the effect of pseudo differential operation. Although it uses only single-ended inputs (A, B), because of this feedback aspect, the circuit has many of the advantages of a differential circuit such as low-voltage operation, higher immunity to noise, and less sensitivity to parasitic elements.

Abstract: A method and apparatus for allowing hot docking of a portable computer (15) into a docking station (20) comprising the steps of making a physical connection (210) between the computer (15) and the docking station (20) wherein the docking station (20) is communicably linked (44) to one or more peripheral devices (35, 40). A system interrupt signal is generated (240) and detected (250) by the system processor (17) causing all activity along the connection path between the computer (15) and the docking station (20) to be suspended (250).

Abstract: The improved Class AB input stage monitors the needs of base current in the slewing transistors 22-25 and supplies that base current with extremely fast and precise feedback loops 90-93. This allows the input stage quiescent current to be very small and gets rid of the non-linearities associated with the lack of base current available to drive the slewing transistors 22-25 in a conventional prior art Class AB input stage. The input stage is a very efficient, low distortion, high small signals and full power bandwidth Class AB input stage.

Abstract: An integrated code development tool, comprising of an editor, a project management and build system, a debugger, a profiler, and a graphical data visualization system. The editor is operable to provide a source code view which is simultaneously capable of integrating with said debugger to provide for stepping through code and setting breakpoints, and integrating with the output of said build system to display source code interleaved with corresponding assembler code created by said build system.

Abstract: A subsampling receiver (50, 50′, 50″) for converting an RF signal to baseband is disclosed. The subsampling receiver (50, 50′, 50″) may be implemented into a wireless communications device (40), such as a wireless telephone handset. In one disclosed embodiment, the receiver (50) includes a sample and hold circuit (80) that samples a bandpass filtered input modulated signal at the subsampling frequency (fs) that is well below the RF carrier frequency but twice the bandwidth (BW) of the payload; the sampled signal is digitized, and applied to two digital mixers (85I, 85Q) to produce in-phase and quadrature components (I,Q) of the payload. In another embodiment, the receiver (50′) includes two sample and hold circuits (96I, 96Q) to sample the filtered signal at different phases of the sampling frequency, to produce the in-phase and quadrature digital components.

Abstract: A plastic land-grid array package, a ball-grid array package, and a plastic leaded package for micromechanical components are fabricated by a molding process characterized by lining the cavity surfaces of the top and bottom mold halves with a protective plastic film, which also protects the surfaces of the components during the molding phase, selectively encapsulating the bonding pads and coupling members of the chip while leaving empty space above the components, and attaching a lid over the components. A molding method as well as a molding apparatus are provided compatible with the sensitivity of the micromechanical devices, yet flexible with regard to the technique used to assemble the chip and the substrate. Furthermore, the method disclosed is flexible with regard to the material and the properties of the substrate.

Abstract: A method for detecting and screening integrated circuit devices having all leads in a row out of planarity specification wherein the leads are deformed at the same angle is described. The method enables existing top-view visual inspection systems to accurately measure the lead span of multiple leads on a plurality of good devices from a product lot, calculate the planarity and tolerances, measure the lead span of each device under test, and from the lead span differences calculate the planarity, and screen devices which are outside the defined tolerances. Technical advantages of this recursive computational procedure assure capture of failed devices having a previously undetectable fault without exceeding the manufacturing capability and specification for the particular device.

Abstract: Wafer cleaning systems (10, 25) utilizing both chemical and physical action to clean integrated circuit wafers (14, 24) is disclosed. Chemical cleaning action is provided by liquid retained within a tank (2, 22), sized either to hold a single wafer (24) or a batch of wafers (14) held within a carrier (12). Physical action is provided in the wafer cleaning system either by way of inert gas bubbling through a baffle (5) or by way of ultrasonic energy applied by transducers (28) located in the tank (2, 22). The systems (10, 25) have a programmable controller (20, 30) for initiating the physical cleaning action after insertion of the wafers (14, 24) into the chemical bath, and for ceasing the physical action prior to removal of the wafers (14, 24). After a waiting time after the ceasing of the physical action, to calm the chemical bath and to permit any retained bubbles to escape to the atmosphere, the wafers (14, 24) may then be removed from the chemical bath, with reduced risk of staining and particle release.

Abstract: A comparator comparing a differential input signal (represented by INM and INP single ended signals) with a differential reference signal (REFP and REFM) to generate a comparison result. The result may be amplified by a desired high amplification factor while consuming minimal electrical power. The comparator may contain two regenerative latches, with each latch containing two terminals. The INM, INP, REFP, and REFM are provided on the four terminals via respective switches. The first and second terminals of the first regenerative latch may respectively be connected to the first and second terminals of the second regenerative latch, with a switch in the path of each connection. The switches may be operated and the regenerative latches may be enabled for a short duration, to generate an amplified comparison result.

Abstract: A package for a semiconductor die having a header with a cavity. The cavity includes a floor, sidewalls and a plurality of vertically spaced apart rows along the cavity sidewalls, each row including a plurality of spaced apart bond fingers. An electrically insulating membrane, preferably silicon, is disposed over the floor of the cavity, the membrane including a plurality of bumps, a plurality of peripherally located membrane bond pads and an interconnect from each of the bumps to a membrane bond pad. Bond wires are connected between the membrane bond pads and the bond fingers on the plurality of rows. A semiconductor die is provided having a plurality of bond pads, each bond pad contacting one of the bumps on the membrane. The header includes a plurality of alternating layers of electrically conducting material and electrically insulating material, the bond fingers on the header each being coupled to one of the layers of electrically conducting material.

Abstract: A fluid pressure sensor (10) has a generally polyhedron configured capacitive transducer (18) electrically connected to a flexible circuit using interference fit U-shaped edge connectors (20). The flexible circuit (16) is received in an electronics chamber formed in a top end of a base member (12) with the corners of the transducer disposed on the face surface (12f) of the top. A cover (24) is formed with a circular fluid pressure opening (24a) through which a sealing gasket (22) extends, the gasket having tabs (22a) received in a seat (24c) formed in the bottom surface of the top wall (24b) of the cover. A transducer receiving seat (24d) is also formed in the bottom surface of the cover for placement of transducer (18).

Abstract: Silicon carbide layers are often used as hardmask layers in semiconductor processing. The photoresist used to pattern the silicon carbide layers during the hardmask patterning process can become poisoned by the silicon carbide layer and remain attached to the silicon carbide surface. According to the method of the instant invention a trimethylsilane and oxygen treatment of the silicon carbide growth chamber prior to layer growth will reduce the photoresist poisoning.

Abstract: A wireless local loop apparatus and corresponding system having an improved DAC operable at higher speed than heretofore achievable which exploits the sigma-delta principle in a different way. More particularly, the invention comprises a wireless local loop terminal (302) and corresponding system (300) that implement a digital-to-analog conversion circuit (105) including a storage means (110), such as a read only memory, for storing delta-sigma analog sequences corresponding to all possible values of a digital input (106) coupled to a plurality of one-bit digital to analog converters (120, 122, 124, 126). Each of the digital-to-analog converters (120, 122, 124, 126) are clocked by multi-phase clocks, such that each phase applied to each one of the digital-to-analog converters (120, 122, 124, 126) is delayed with respect to one another by the oversampling period.

Abstract: A security system to prevent unauthorized starting of the engine of a vehicle has a remote control unit (18) equipped with a transponder which, on reception of an interrogation signal using at least one reception aerial (20), transmits an identification code group using a transmitter unit (40). Located in the vehicle is a control unit (12), which on actuation of a starter button (26) within the vehicle, transmits the interrogation signal, and subsequently checks the identification code group transmitted by the remote control unit. Starting of the engine will only be possible when the identification code group coincides with the code group expected by it. Connected to the reception aerial (20) is a signal detector (28), which has a reaction threshold level that can be toggled between a high value and a low value. This signal detector will relay the interrogation signal to further processing stages only when the interrogation signal level exceeds the set reaction threshold.

Abstract: A circuit (50) and method are presented to provide positive biasing voltages to an MR head (18) in a mass data storage device (10). The circuit (50) includes upper (56) and lower (62) driver transistors to respectively bias respective opposite ends of the MR head (18) with positive voltages. A feedback circuit (58,60,74,84) controls a lower voltage (63) of the positive voltages to be a value as close as possible to a saturation voltage of the lower driver transistor (62), without causing the lower transistor (62) to saturate. Since the MR head (18) is connected between the upper (56) and lower (62) driver transistors, maintaining the lower voltage (63) just above the saturation voltage of the lower driver transistor (62) reduces the common mode voltage across the MR head (18) to a minimum value.

Abstract: A protocol and associated circuitry operable for efficiently extending serial bus capability in system environments is disclosed. The protocol is designed to coexist and be fully compatible with existing serial bus approaches, and in particular an example of application of the invention to a backplane system utilizing the 1149.1 IEEE standard serial bus is detailed. The circuitry and protocol required to couple any one of the boards on the backplane to the serial bus master without modifying the existing serial bus protocol, without adding additional signals, and without affecting the throughput rate of the serial bus is described. The invention advantageously allows the serial bus master to select, communicate with, and deselect backplane boards so that high level test functions may be simultaneously executed and monitored. Additional preferred embodiments are also disclosed.

Abstract: A method and apparatus for improving an S/N ratio in a digital-to-analog conversion of a PDM signal are provided. A digital-to-analog conversion system comprises an S/N ratio improving section. The S/N ratio improving section has a signal component extractor which extracts a signal component included in the PDM signal, and outputs a digitally filtered output signal. The digitally filtered output signal has a second full scale smaller than a first full scale of the PDM signal. The S/N ratio improving section also comprises a full-scale matching unit which matches the second full scale of the digitally filtered output signal with a third full scale of digital-to-analog conversion.

Abstract: A transceiver (100) such as used in Discrete Multitone (DMT) modulation of digital signals for communication, such as in a DSL modem communications system, is described. The transceiver (100) includes a function (119) by way of which unloaded subchannels are encoded with a clip prevention signal. The clip prevention signal is derived to avoid clipping by an amplifier (18) after modulation into the time domain, upsampling, and filtering. The effects of the upsampling and filtering are considered in deriving the clip prevention signal, by considering the upsampling and filtering as a polyphase combination, and using the filter response for each phase. Frequency domain and time domain update alternatives are disclosed.

Abstract: A method of forming a memory device (e.g., a DRAM) including array and peripheral circuitry. A plurality of undoped polysilicon gates 58 are formed. These gates 58 are classed into three groups; namely, first conductivity type peripheral gates 58p, second conductivity type peripheral gates 58n, and array gates 58a. The array gates 58a and the first conductivity type peripheral gates 58n are masked such that the second conductivity type peripheral gates 58p remain unmasked. A plurality of second conductivity type peripheral transistors can then be formed by doping each of the second conductivity type peripheral gates 58p, while simultaneously doping a first and a second source/drain region 84 adjacent each of the second conductivity type peripheral gates 58p. The second conductivity type peripheral gates 58p are then masked such that the first conductivity type peripheral gates 58n remain unmasked.

Abstract: An embodiment of the instant invention is a method of forming a conductive contact to a top electrode (308 and 310 of FIG. 4d) of a ferroelectric capacitor comprised of a bottom electrode (304 of FIG. 4d) situated under the top electrode and a ferroelectric material (306 of FIG. 4d) situated between the top electrode and the bottom electrode, the method comprising the steps of: forming a layer (408 or 312 of FIG. 4) over the top electrode; forming an opening (414 of FIG. 4d) in the layer to expose a portion of the top electrode by etching the opening into the layer using a hydrogen-free etchant; and depositing conductive material (432 of FIG. 4d) in the opening to form an electrical connection with the top electrode.