Abstract: One aspect of the invention is an integrated circuit (10 or 110) comprising an amplifier (11 or 111) having at least two poles in its frequency response and an output impedance compensation circuit (M1A, M2, M3, AC1 or M1A, M2, M3, M4, AC1) coupled to an output node (30) of the amplifier (11 or 111). The output impedance compensation circuit (M1A, M2, M3, AC1 or M1A, M2, M3, M4, AC1) is operable to create a feedback signal proportional to the impedance of an output load (50) coupled to the output node (30), and create a zero in the frequency response of the amplifier (11 or 111) in response to the feedback signal between the at least two poles.

Abstract: An embodiment of the instant invention is a method of forming a conductive contact to a top electrode (308 and 310 of FIG. 4d) of a ferroelectric capacitor comprised of a bottom electrode (304 of FIG. 4d) situated under the top electrode and a ferroelectric material (306 of FIG. 4d) situated between the top electrode and the bottom electrode, the method comprising the steps of: forming a layer (408 or 312 of FIG. 4) over the top electrode; forming an opening (414 of FIG. 4d) in the layer to expose a portion of the top electrode by etching the opening into the layer using a hydrogen-free etchant; and depositing conductive material (432 of FIG. 4d) in the opening to form an electrical connection with the top electrode.

Abstract: A way to combine the metal bitline with the vertical interconnection to the capacitor over the bitline. In this class of embodiments, the vertical interconnect pillar is formed before fabrication of the bitline is completed. To accomplish this, the bitline metal is patterned using a step which allows it to extend vertically along the walls of the vertical interconnect pillar, but does not create any electrical connection between the bitline metal and the vertical interconnect pillar.

Abstract: CMOS semiconductor pass-transistor logic circuitry (200) is disclosed, comprising pass transistor circuitry (204, 212, 218), and tunneling structure circuitry (228) coupled to the pass transistor circuitry; where the tunneling structure circuitry is adapted to hold a node (222) voltage stable by compensating a leakage current (302) originating from said pass transistor circuitry.

Abstract: A structure for, and method of forming, a metal-insulator-semiconductor field-effect transistor in an integrated circuit is disclosed. The disclosed method comprises forming a germanium layer 52 on a semiconductor substrate (e.g. silicon 20), depositing a large-permittivity gate dielectric (e.g. tantalum pentoxide 56) on the germanium layer, and forming a gate electrode (e.g., titanium nitride 60) on the gate dielectric. The method may comprise forming source and drain regions 64 in the substrate on either side of the gate dielectric. The germanium layer, which is preferably epitaxially grown, generally prevents formation of a low dielectric constant layer between the gate dielectric and the semiconductor substrate. The disclosed structure comprises a germanium layer 52 disposed on a semiconductor substrate (e.g. silicon 20), a large-permittivity gate dielectric (e.g. tantalum pentoxide 56) disposed on the germanium layer, and a gate electrode (e.g., titanium nitride 60) disposed on the gate dielectric.

Abstract: A system for project management integration includes a design database having design data stored in a hierarchical manner representable by design hierarchical data. The system further includes a schedule database having scheduling data stored in a hierarchical manner representable by schedule hierarchical data. The system also includes an integration module in communication with the design database and the schedule database, the integration module operable to compare the design hierarchical data and the schedule hierarchical data in response to changes to one of the design or schedule databases, the integration module further operable to change one of the design and schedule databases in response thereto.

Abstract: A method for providing a sample-rate conversion (“SRC”) filter on an input stream of sampled data provided at a first rate, to produce an output stream of data at a second rate different from the first rate. The input stream of sampled data is operated on with a first low-order interpolation filter routine to produce a first stream of intermediate data. The first stream of intermediate data is operated on with a first simplified interpolation filter routine, having a substantially small number of operations to calculate the coefficients thereof, to produce a second stream of intermediate data. The second stream of intermediate data is operated on with a first decimating filter routine to produce the output stream of data.

Abstract: A CDAC circuit is provided that can operate at low supply voltages, for example, at supply voltages of 2.5 volts or less. To accomplish low voltage operation, switches in the CDAC circuit, such as sampling bit switches, mid-point switches or auto-zero switches, are gate-boosted to permit the voltage at the transmission gates to exceed the threshold voltage and thus permit the transmission gates to effectively operate. As a result, the CDAC can continue to operate, even with the existence of lower power supply voltages. In accordance with an exemplary embodiment, a gate-boosting circuit comprises a pair of N-channel transistor devices and a charging capacitor configured to provide a gate-boosting voltage to the transmission gates. In addition, the gate boosting circuit can comprise conventional CMOS devices, rather than more expensive low threshold MOSFET devices.

Abstract: An integrated circuit having improved soft error protection and a method improving the soft error protection of an integrated circuit are disclosed. The integrated circuit comprises a substrate 72, a transistor formed in the substrate 72, a first region 74 (e.g. a well) formed in the substrate having a first conductivity type, a second region 84 below the first region 74 having a second conductivity type, and a trench formed in the substrate having a depth at least substantially as deep as the well. The trench 70 is filled with a non-conductive material 71 that forms a frame around the transistor, whereby soft errors due to electron-hole pairs caused by ionizing radiation in the frame are substantially eliminated.

Abstract: A CMOS programmable gain amplifier (10) is disclosed which provides exponential gain using a single gain element (19) which may be implemented in either bipolar or CMOS technology. An embodiment of the present invention includes a first and second sampling impedance (12, 14), a first and second feedback impedance (16, 18) and a gain element (19). The gain element (19) having an inverting input, a non-inverting input and an output. The inverting input connects to the first sampling impedance (12). The non-inverting input connects to the second sampling impedance (14). The first feedback impedance (16) connects between the inverting input and the output. The second feedback impedance (18) connects between the non-inverting input and the output.

Abstract: A voltage level shifter with testable cascode devices is disclosed. According to one embodiment, the level shifter includes multiple cascode devices and switches a first output driver according to the values of a data input and an enable input. Testability devices coupled to cascode devices of the level shifter detect a current in response to failure of the corresponding cascode device.

Abstract: A grating (18) couples the waveguide region (36) of a semiconductor laser (11) to a dielectric waveguide (26). The waveguide region of the laser includes a mirror (15) at one end thereof and an absorber (19) at the other end thereof. The dielectric waveguide includes a reflector (24) therein to reflect a portion of the light coupled from the laser to the dielectric waveguide back into the laser waveguide region.

Abstract: A circuit (50) and method are provided for generating a signal (84) indicating an open impedance fault of a coil (56) of a write head (18) of a mass data storage device (10). The circuit (10) includes a differential amplifier (51) with the electrical component (56) being connected as a load in a first leg thereof. An impedance element (64) is provided in a second leg of the differential amplifier (50), and a pair of bipolar transistors (52,54) are respectively connected in the first and second legs. The pair of bipolar transistors (52,54) have a constant bias voltage (Bias) applied to inputs thereof, and an output circuit is connected to an output node of the first leg of the differential amplifier (51).

Abstract: A programmable burst FIFO buffer (100) allows for burst of data to be loaded into memory (106) without the device writing into the buffer having to check on every clock cycle as to whether the buffer is full or not. The buffer (100) is also programmable and allows for “N” words to be loaded with “N” being programmable in any given burst without having to check for a buffer full condition. The buffer (100) also avoids the glitches associated with other buffer designs due to the write and read clock being in different domains.

Abstract: A digital system is provided with an Analog to Digital converter (ADC) that has a configuration that allows a programmable number of Auto conversions to occur on two separate and independent, but cascadeable, sequencers (or state machines). For each conversion state, the sequencer/s can be programmed to arbitrarily select any one of a set of muxed analog input channels. In addition, each conversion state has a unique result register in which the converted value is placed at completion of conversion. This ADC control system gives the capability to set up various forms of input signal sampling strategies. For example, one such strategy samples and converts the same channel multiple times allowing an over-sampling algorithm to be easily performed. By over sampling, increased resolution over traditional single sampled conversion systems can be obtained by suitable processing of the over-sampled results.

Abstract: Two oscillators, such as in two pulse width modulator circuits of DC to DC power converters, are maintained in synchronization and at a predetermined phase shift from one another by a circuit incorporating a comparator. A sawtooth signal output from the master oscillator is fed to one comparator input while the sawtooth signal is filtered and applied to the second input of the comparator to generate an approximately 180° phase shift turn-on at the output of the comparator that is fed through a driver circuit to an input of a second oscillator. By insuring that the faster operating oscillator is the master, the slave oscillator will be triggered by the signal from the master.

Abstract: A method to form asymmetric MOS transistors using a replacement gate design. The method involves forming implanted regions (140) and (145) in the channel region after removal of the replacement gate structure (110) to produce high threshold voltage regions and low threshold voltage regions.

Abstract: A RESURF LDMOS transistor (64) includes a RESURF region (42) that is self-aligned to a LOCOS field oxide region (44). The self-alignment produces a stable breakdown voltage BVdss by eliminating degradation associated with geometric misalignment and process tolerance variation.

Abstract: The present invention relates to a high speed sample and hold circuit which comprises a plurality of sample and hold subcircuits coupled in parallel between an input and an output. The circuit also comprises a calibration circuit coupled to the plurality of sample and hold subcircuits. The calibration circuit is operable to modify a hold signal for one or more of the plurality of sample and hold subcircuits to thereby reduce timing mismatch between the plurality of sample and hold subcircuits and distortion associated therewith. The present invention also comprises a method of reducing timing mismatch in a high speed, parallel coupled sample and hold circuit. The method comprises detecting timing mismatch associated with a plurality of sample and hold subcircuits and modifying a hold signal for one or more of the subcircuits.

Abstract: A data processing apparatus is embodied in a single integrated circuit. The data processing apparatus includes a central processing unit, at least one level one cache, a level two unified cache and a directly addressable memory. The at least one level one cache preferably includes a level one instruction cache temporarily storing program instructions for execution by the central processing unit and a level one data cache temporarily storing data for manipulation by said central processing unit. The level two unified cache and the directly addressable memory are preferably embodied in a single memory selectively configurable as a part level two unified cache and a part directly addressable memory. The single integrated circuit data processing apparatus further includes a direct memory access unit connected to the directly addressable memory and adapted for connection to an external memory. The direct memory access unit controls data transfer between the directly addressable memory and the external memory.