Patents Assigned to Texas Instruments
  • LDMOS device with self-aligned resurf region and method of fabrication
    Patent number: 6483149
    Abstract: A RESURF LDMOS transistor (64) includes a RESURF region (42) that is self-aligned to a LOCOS field oxide region (44). The self-alignment produces a stable breakdown voltage BVdss by eliminating degradation associated with geometric misalignment and process tolerance variation.
    Type: Grant
    Filed: May 14, 1997
    Date of Patent: November 19, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Dan M. Mosher, Taylor R. Efland
  • 4T memory with boost of stored voltage between standby and active
    Patent number: 6483739
    Abstract: In a 4T SRAM cell, voltage states of nodes during transition to active is boosted to provide stability and allow lower power consumption standby states.
    Type: Grant
    Filed: December 31, 2001
    Date of Patent: November 19, 2002
    Assignee: Texas Instruments Incorporated
    Inventor: Theodore W. Houston
  • Failsafe interface circuit with extended drain services
    Patent number: 6483346
    Abstract: Failsafe interface circuits are provided for an integrated circuit having a core logic section providing a signal to, or receiving a signal from, a bond pad connection. The interface circuits employ high voltage tolerant, extended drain devices in circuit arrangements which insure that the stress of a failsafe event is only exhibited by the extended drain devices. A failsafe event is defined as a bond pad voltage which exceeds the supply voltage of the integrated circuit plus the threshold voltage of the transistors within the integrated circuit. Both failsafe output driver circuit and failsafe receiver circuit embodiments are provided.
    Type: Grant
    Filed: January 25, 2002
    Date of Patent: November 19, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Keith E. Kunz, James D. Huffman
  • Low slew rate charge pump
    Patent number: 6483377
    Abstract: The present invention includes a charge pump circuit to raise a voltage including a voltage source to generate the voltage to be raised, a pair of switches to switch the voltage to a capacitor with the first pair of switches operating during different periods of time and a second pair of switches to switch additional voltage to the capacitor with the second pair of switches operating during different periods of time.
    Type: Grant
    Filed: January 10, 2001
    Date of Patent: November 19, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Bertram J. White, Ying Zhang McCleary
  • Method and apparatus for characterizing asymmetries of an MR head
    Patent number: 6483297
    Abstract: A method and apparatus for characterizing asymmetries of a magneto-resistive type head in proximity to a magnetic media such as a magnetic disk of a hard disk drive. The method includes using the magneto-resistive type head to read a continuous signal from the magnetic media to provide a read back signal. Energies contained in the read back signal which occur in excess of a predetermined threshold for the positive and negative portions of the read back signal are then determined. The energies may be determined by accumulating sampled signal values from the read back signal in registers during times at which the read back signal exceeds the threshold.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: November 19, 2002
    Assignee: Texas Instruments Incorporated
    Inventor: Charles H. Sobey
  • Shot averaging for fine pattern alignment with minimal throughput loss
    Patent number: 6482713
    Abstract: A way to average alignment measurements that obtains the advantage of multiple alignment marks per shot without requiring actual measurement of all alignment marks on all wafers of a batch. All alignment marks on all sampled shots are measured and averaged on the first wafer of a batch. The offset between a single sampled alignment mark and the average total offset for the wafer is characterized and applied when that alignment mark is sampled on succeeding wafers.
    Type: Grant
    Filed: July 19, 2001
    Date of Patent: November 19, 2002
    Assignee: Texas Instruments Incorporated
    Inventor: Edward J. Marini
  • DC/DC converter
    Patent number: 6483282
    Abstract: A charge pump-type DC/DC converter comprises n (n≧2) elementary stages, each consisting of a charge pump capacitor and several controllable switches connected thereto, whereby the input voltage of the DC/DC converter is applied to the input of the first stage, both electrodes of the charge pump capacitor of the kth stage are each connectable to one of the controllable switches with the output of the (k−1)th stage, k=2, . . . , n and the output of the nth stage forms the output of the DC/DC converter. The DC/DC converter in accordance with the invention is characterized in that it in addition enables one or more further controllable switches to be connected, via which the electrode of the charge pump capacitor of the nth stage which in the discharge phase is not connected to the output of the converter, to one or more outputs of the 1th stage (1=(n−2), . . .
    Type: Grant
    Filed: September 13, 2001
    Date of Patent: November 19, 2002
    Assignee: Texas Instruments Deutschland, GmbH
    Inventor: Erich Bayer
  • Utilizing amorphorization of polycrystalline structures to achieve T-shaped MOSFET gate
    Patent number: 6482688
    Abstract: A method of forming a generally T-shaped structure. The method comprises forming a poly/amorphous silicon layer stack which comprises a polysilicon layer and a generally amorphous silicon layer overlying the polysilicon layer. The method further comprises selectively etching the poly/amorphous silicon layer stack, wherein an etch rate associated with the generally amorphous silicon layer in an over etch step associated therewith is less than an etch rate associated with the polysilicon layer, thereby causing a lateral portion of the generally amorphous silicon layer to extend beyond a corresponding lateral portion of the polysilicon layer.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: November 19, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Chimin Hu, Amitabh Jain, Reima Tapani Laaksonen, Manoj Mehrotra
  • Method for improving direct memory access performance
    Patent number: 6484218
    Abstract: A serial bus controller having improved bus performance when a physical read request or a physical write request is present. A link and physical layer logic unit is provided, coupled to a serial bus having at least one peripheral device coupled thereto. A host interface is provided, coupled to a host data bus. A request FIFO is provided, coupled to receive a host memory read or write request packet from the link and physical layer logic unit, and coupled to said host interface. A physical read request FIFO is provided, coupled to receive a physical read request from the request FIFO for further processing of the physical read request. A physical write request FIFO is provided, coupled to receive a physical write response for transfer to the peripheral device.
    Type: Grant
    Filed: October 1, 1999
    Date of Patent: November 19, 2002
    Assignee: Texas Instruments Incorporated
    Inventor: Randall E. Pipho
  • Statistics signature generation and analysis
    Patent number: 6484288
    Abstract: The present invention provides for a statistics Cyclic Redundancy Check (CRC) (108) wherein the statistics CRC (108) is representative of the values contained within a statistics RAM (110). The statistics CRC (108) is then used to reduce test vectors by allowing the validity of the statistics to be determined by reading this signature instead of reading all the individual statistics. The signature is regenerated for each complete pass of the statistics, and the contents of this register are only updated when the pass is complete.
    Type: Grant
    Filed: December 17, 1999
    Date of Patent: November 19, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Christopher J. Hall, Robert J. Harrison, Anthony S. Rowell, Amarjit S. Bhandal
  • Method and device for automated transfer and maintenance of internet based information
    Patent number: 6484198
    Abstract: A method of transferring electronic equivalents (32) of published items (18) is provided wherein bar codes (116, 118) are attached on the items (18) prior to distribution to subscribers (12). The bar codes (116, 118) are scanned by a bar code reader (22), formatted into a predetermined message format compatible with network protocols and transmitted to the associated publishing authority (30). Based on the bar code information, the publisher (30) will either push the requested electronic equivalent (32) or transfer a pointer to the user (12) to a network cite containing the requested electronic equivalent (32). Alternatively, the publisher (30) can push updates of published items (32) to users (12).
    Type: Grant
    Filed: February 10, 1999
    Date of Patent: November 19, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Rajko Milovanovic, Bharathi Subramanian
  • High density and high speed cell array architecture
    Patent number: 6483131
    Abstract: The present invention provides an array of customizable functional cells having high density and high drive capacity. It further provides an architecture that maximizes the width of P-channel transistors in an array of standard cells to compensate for the lower speed operation of P-type devices. More particularly, the invention discloses a digital circuit comprising a plurality of inputs for receiving respective logic signal and circuitry, coupled to the inputs, for passing one of the signals responsive to the order in which a transition is received on each of the inputs.
    Type: Grant
    Filed: December 14, 2000
    Date of Patent: November 19, 2002
    Assignee: Texas Instruments Incorporated
    Inventor: U-Ming Ko
  • Creep acting miniature thermostatic electrical switch and thermostatic member used therewith
    Patent number: 6483418
    Abstract: A creep acting thermostatic switch (30) has an oblong, electrically conductive cup-shaped housing (32) formed with a side wall (32b) extending upwardly from a bottom wall (32a). A generally J-shaped creep acting thermostatic member (38) has a short leg (38a) attached to the side wall, a long leg (38b) extending across the cavity formed in the housing and a bight portion between the legs having a flattened surface portion (38c) to prevent interference with the corner between the side wall and bottom wall. A movable electrical contact (40) is mounted on the free end of the long leg and is movable into and out of engagement with a stationary electrical contact (37) mounted on a lid (36) received on the side wall. This arrangement allows for a thermostatic member having an optimized length to width ratio to provide maximum disc forces for a given housing size.
    Type: Grant
    Filed: August 18, 2000
    Date of Patent: November 19, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Debra E. Reno, Brian J. Simoes, George R. Holman
  • Semiconductor memory device and manufacturing method thereof
    Patent number: 6483141
    Abstract: In a DRAM with a COB (capacitor over bitline) structure where one side of the storage node is approximately equal to the diameter of the contact plug, when the mask is mis-positioned when the storage node is formed, to prevent the underlying oxide film from being exposed at the side surface of the contact hole and to prevent that underlying oxide film from being inadvertently etched during wet etching. Contact plug 7 is formed with oxide film 20 attached on nitride film 5, that acts as an etching stopper during wet etching. By doing this, contact plug 7 is formed projecting upward above underlying oxide film 4 and preferably projecting above nitride film 5. After storage node 10 is formed, when oxide films 8 and 20 are removed by wet etching, underlying oxide film 4 is not exposed at the side surface of contact hole 6 and inadvertent etching of it can be prevented.
    Type: Grant
    Filed: August 30, 1999
    Date of Patent: November 19, 2002
    Assignee: Texas Instruments Incorporated
    Inventor: Michiaki Sano
  • Parallel data test for a semiconductor memory
    Patent number: 6484289
    Abstract: A semiconductor memory device having a parallel data test scheme is disclosed. The semiconductor memory includes an array that is partitioned into array portions with each array portion further divided into sub-arrays and banks. Each array portion providing data bits to a data compression circuit. The data compression circuit includes data compare sections and ripple sections. The data compare sections include data compare circuits that compare the data bits provided by each array portion and each provide a compare output to the ripple sections. The ripple sections are coupled together in series and provide global data compare outputs. A multiplexer selects between a data bit and the global data compare outputs to provide either a data output or a data comparison output to the output pin.
    Type: Grant
    Filed: September 23, 1999
    Date of Patent: November 19, 2002
    Assignee: Texas Instruments Incorporated
    Inventor: Kuo-yuan Hsu
  • High speed amplifier
    Patent number: 6483384
    Abstract: The object of this invention is to realize high-speed rise and/or fall characteristics for amplifier without increasing transistor size or current consumption. A first rise sensing circuit 42 and a second a sensing circuit 44 are connected to main circuit 40. The first sensing circuit 42 has a PMOS transistor which functions as a rise sensing transistor, a pair of NMOS transistors 48 and 50, which form a current-mirror circuit, and a PMOS transistor 52, which drives the PMOS transistor 46 used for speed up in main circuit 40. The second sensing circuit 44 has a PMOS transistor 54, which functions as a fall sensing transistor, a pair of NMOS transistors 56 and 58, which form a current-mirror circuit, and a PMOS transistor 60 used for driving the PMOS transistor used for speed up in main circuit 40.
    Type: Grant
    Filed: May 16, 2001
    Date of Patent: November 19, 2002
    Assignee: Texas Instruments Incorporated
    Inventor: Tsuyoshi Chimura
  • CDMA mobile communications system and method with improved channel estimation and pilot symbol transmission
    Patent number: 6483821
    Abstract: The present invention is an improved system and method for transmitting and receiving digital information over mobile communication channels. The present invention includes an enhanced channel estimator (34) which iteratively estimates channel amplitude and phase distortion from received pilot and data signal information at various time instants. The iterative channel estimation scheme of the present invention provides increased performance of the transceiver system which allows for efficiencies such as transmission of a minimal amount of pilot information and reduction in the transmitted power.
    Type: Grant
    Filed: April 19, 1999
    Date of Patent: November 19, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Anand G. Dabak, Srinath Hosur, Timothy Schmidl
  • System and method for classifying an anomaly
    Patent number: 6483938
    Abstract: A method and system for generating and managing a knowledgebase for use in identifying anomalies on a manufactured object, such as a semiconductor wafer, includes measures for adding, deleting, and organizing data from the knowledgebase.
    Type: Grant
    Filed: March 6, 2000
    Date of Patent: November 19, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: A. Kathleen Hennessey, YouLing Lin, Rajasekar Reddy, C. Rinn Cleavelin, Howard V. Hastings, II, Pinar Kinikoglu, Wan S. Wong
  • Low cost multiplier block with chain capability
    Patent number: 6484194
    Abstract: This application describes a method of multiplying numbers represented in multiple-word chains. The multiplication scheme allows for the multiplication of both signed and unsigned numbers of varying lengths. The multiplier block 30 executes a 17-bit by 17-bit two's complement multiply and multiply-accumulate in a single instruction cycle. A 4-bit shift value register with a 4 to 16 bit decoder 35 allows the multiplier to do a 1-16 bit barrel shift on either a 16-bit operand or an (N×16)-bit chain operand.
    Type: Grant
    Filed: June 17, 1999
    Date of Patent: November 19, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Alva Henderson, Francesco Cavaliere
  • Compare path bandwidth control for high performance automatic test systems
    Patent number: 6479985
    Abstract: The compare path bandwidth control for high performance automatic test systems provides a standard dual comparator mode with single ended transmission lines for low frequency applications with a capability of receiving a differential signal when using the dual comparators (40), (41) as an effective single comparator for high frequency applications.
    Type: Grant
    Filed: June 1, 2001
    Date of Patent: November 12, 2002
    Assignee: Texas Instruments Incorporated
    Inventor: Craig J. Lambert